diff options
| author |   Rhyland Klein <rklein@nvidia.com> | 2015-06-18 17:28:21 -0400 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2015-11-20 18:04:35 +0100 |
| commit | 204c85d124bd51c0b1c70f1d6b0d853389179d38 (patch) | |
| tree | b4397111003a5bedc24763882b1bc1aea418c473 /drivers/clk/tegra/clk-pll.c | |
| parent | clk: tegra: pll: Simplify clk_enable_path (diff) | |
| download | wireguard-linux-204c85d124bd51c0b1c70f1d6b0d853389179d38.tar.xz wireguard-linux-204c85d124bd51c0b1c70f1d6b0d853389179d38.zip | |
clk: tegra: pll: Update warning message
Swap out the generic WARN_ON with a WARN which gives more information
about what is happening.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 6c29ad7e15e7..79f4dc230dee 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -692,7 +692,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, pdiv = _hw_to_p_div(hw, cfg.p); if (pdiv < 0) { - WARN_ON(1); + WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", + __clk_get_name(hw->clk), cfg.p); pdiv = 1; } |