diff options
| author |   Bill Huang <bilhuang@nvidia.com> | 2015-06-18 17:28:38 -0400 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2015-12-17 13:37:57 +0100 |
| commit | a4ca2b2fe7252032022d14b4efd462161c91165b (patch) | |
| tree | b7752b39cefa957f4e0cbc6821df27c5916d6f5a /drivers/clk/tegra/clk-pll.c | |
| parent | clk: tegra: pll: Fix issues with rates for VCO PLLs (diff) | |
| download | wireguard-linux-a4ca2b2fe7252032022d14b4efd462161c91165b.tar.xz wireguard-linux-a4ca2b2fe7252032022d14b4efd462161c91165b.zip | |
clk: tegra: Fix WARN_ON in PLL_RE registration
This fixes two things.
- Read the correct IDDQ register
- Check the correct IDDQ bit position
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 731c6857c895..9ca1120262f0 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1735,7 +1735,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, val = pll_readl_base(pll); if (val & PLL_BASE_ENABLE) - WARN_ON(val & pll_params->iddq_bit_idx); + WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & + BIT(pll_params->iddq_bit_idx)); else { int m; |