diff options
| author |   Alexandre Courbot <acourbot@nvidia.com> | 2013-11-21 03:38:10 +0100 |
|---|---|---|
| committer |   Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 18:46:57 +0200 |
| commit | 5ab5d4048e6ed8811245a4ea45264456c180545e (patch) | |
| tree | 1c7b1a386a1d1137c4980858a79e7aa9de72a208 /drivers/clk/tegra/clk-tegra20.c | |
| parent | clk: tegra: Properly setup PWM clock on Tegra30 (diff) | |
| download | wireguard-linux-5ab5d4048e6ed8811245a4ea45264456c180545e.tar.xz wireguard-linux-5ab5d4048e6ed8811245a4ea45264456c180545e.zip | |
clk: tegra: add FUSE clock device
This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index be5bdbab78a6..b3b7204acfe7 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -446,6 +446,7 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK }, { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK }, { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK }, + { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE }, { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD }, { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO }, { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X }, |