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| author |   Rhyland Klein <rklein@nvidia.com> | 2015-06-18 17:28:23 -0400 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2015-11-20 18:05:02 +0100 |
| commit | 3706b43629f5b9fd4efce192da40ffa9412e75ee (patch) | |
| tree | 51dd671dcc551fbfdedf544179413acd019dcf63 /drivers/clk/tegra/clk.h | |
| parent | clk: tegra: pll: Change misc_reg count from 3 to 6 (diff) | |
| download | wireguard-linux-3706b43629f5b9fd4efce192da40ffa9412e75ee.tar.xz wireguard-linux-3706b43629f5b9fd4efce192da40ffa9412e75ee.zip | |
clk: tegra: pll: Don't unconditionally set LOCK flags
SoC specific drivers should define the appropriate flags for each
PLL rather than relying on the registration functions to automatically
set flags on their behalf. This will properly allow for changes between
SoC generations where flags might be different and allow sharing the
same logic functions.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
0 files changed, 0 insertions, 0 deletions