diff options
| author |   Peter De Schrijver <pdeschrijver@nvidia.com> | 2018-01-25 16:00:11 +0200 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2018-03-08 15:26:54 +0100 |
| commit | cbfc8d0a85aa72ad66227c69b08904143dc73bbb (patch) | |
| tree | e960966788a66c4f6e9e4fc740d5de4c179b25b6 /drivers/clk/tegra/clk.h | |
| parent | clk: tegra: Add la clock for Tegra210 (diff) | |
| download | wireguard-linux-cbfc8d0a85aa72ad66227c69b08904143dc73bbb.tar.xz wireguard-linux-cbfc8d0a85aa72ad66227c69b08904143dc73bbb.zip | |
clk: tegra: add fence_delay for clock registers
To ensure writes to clock registers have properly propagated through the
clock control logic and state machines, we need to ensure the writes have
been posted in the registers and wait for 1us after that.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Hector Martin <marcan@marcan.st>
Tested-by: Andre Heider <a.heider@gmail.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 3b2763df51c2..ba7e20e6a82b 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -812,4 +812,11 @@ int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); +/* Combined read fence with delay */ +#define fence_udelay(delay, reg) \ + do { \ + readl(reg); \ + udelay(delay); \ + } while (0) + #endif /* TEGRA_CLK_H */ |