diff options
| author |   Thierry Reding <treding@nvidia.com> | 2023-06-30 15:07:48 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2023-07-04 08:54:37 -0700 |
| commit | f679e89acdd3e825995a84b1b07e2ea33ea882ee (patch) | |
| tree | 0917269f6bd621416fa32690f960df021d926dea /drivers/clk/tegra | |
| parent | dt-bindings: mfd: ti,j721e-system-controller: Remove syscon from example (diff) | |
| download | wireguard-linux-f679e89acdd3e825995a84b1b07e2ea33ea882ee.tar.xz wireguard-linux-f679e89acdd3e825995a84b1b07e2ea33ea882ee.zip | |
clk: tegra: Avoid calling an uninitialized function
Commit 493ffb046cf5 ("clk: tegra: super: Switch to determine_rate")
replaced clk_super_round_rate() by clk_super_determine_rate(), but
didn't update one callsite that was explicitly calling the old
tegra_clk_super_ops.round_rate() function, which was now NULL. This
resulted in a crash on Tegra30 systems during early boot.
Switch this callsite over to the clk_super_determine_rate() equivalent
to avoid the crash.
Fixes: 493ffb046cf5 ("clk: tegra: super: Switch to determine_rate")
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20230630130748.840729-1-thierry.reding@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/tegra')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra-super-cclk.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c index 68d7bcd5fc8a..3b22a4d0dffc 100644 --- a/drivers/clk/tegra/clk-tegra-super-cclk.c +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -86,9 +86,18 @@ static int cclk_super_determine_rate(struct clk_hw *hw, if (rate <= pllp_rate) { if (super->flags & TEGRA20_SUPER_CLK) rate = pllp_rate; - else - rate = tegra_clk_super_ops.round_rate(hw, rate, - &pllp_rate); + else { + struct clk_rate_request parent = { + .rate = req->rate, + .best_parent_rate = pllp_rate, + }; + + clk_hw_get_rate_range(hw, &parent.min_rate, + &parent.max_rate); + tegra_clk_super_ops.determine_rate(hw, &parent); + pllp_rate = parent.best_parent_rate; + rate = parent.rate; + } req->best_parent_rate = pllp_rate; req->best_parent_hw = pllp_hw; |