diff options
| author |   Rajan Vaja <rajan.vaja@xilinx.com> | 2021-06-28 00:01:19 -0700 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2021-06-28 23:35:36 -0700 |
| commit | 610a5d83010eaf02a857321092cf0cd02178bee7 (patch) | |
| tree | 427744497ebac2f22c007e2c3c4a5f0e9b0e2e5a /drivers/clk/zynqmp/clk-zynqmp.h | |
| parent | clk: zynqmp: pll: Remove some dead code (diff) | |
| download | wireguard-linux-610a5d83010eaf02a857321092cf0cd02178bee7.tar.xz wireguard-linux-610a5d83010eaf02a857321092cf0cd02178bee7.zip | |
clk: zynqmp: Use firmware specific common clock flags
Currently firmware passes CCF specific flags to ZynqMP clock driver.
So firmware needs to be updated if CCF flags are changed. The firmware
should have its own 'flag number space' that is distinct from the
common clk framework's 'flag number space'. So define and use ZynqMP
specific common clock flags instead of using CCF flags.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Link: https://lore.kernel.org/r/20210628070122.26217-2-rajan.vaja@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/zynqmp/clk-zynqmp.h')
| -rw-r--r-- | drivers/clk/zynqmp/clk-zynqmp.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h index 5beeb41b29fa..aa013a59c7cc 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -10,6 +10,20 @@ #include <linux/firmware/xlnx-zynqmp.h> +/* Common Flags */ +/* must be gated across rate change */ +#define ZYNQMP_CLK_SET_RATE_GATE BIT(0) +/* must be gated across re-parent */ +#define ZYNQMP_CLK_SET_PARENT_GATE BIT(1) +/* propagate rate change up one level */ +#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2) +/* do not gate even if unused */ +#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3) +/* don't re-parent on rate change */ +#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7) +/* do not gate, ever */ +#define ZYNQMP_CLK_IS_CRITICAL BIT(11) + enum topology_type { TYPE_INVALID, TYPE_MUX, @@ -33,6 +47,8 @@ struct clock_topology { u8 custom_type_flag; }; +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag); + struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, const char * const *parents, u8 num_parents, |