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| author |   Seiya Wang <seiya.wang@mediatek.com> | 2019-02-25 14:51:12 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2019-02-26 10:17:40 -0800 |
| commit | 64f4466c887e2f16cb01467c8064ff1106c980a3 (patch) | |
| tree | 7c9668c4bd09e63a5e586818a16b34ea89c8bf5e /drivers/clk | |
| parent | Linux 5.0-rc1 (diff) | |
| download | wireguard-linux-64f4466c887e2f16cb01467c8064ff1106c980a3.tar.xz wireguard-linux-64f4466c887e2f16cb01467c8064ff1106c980a3.zip | |
clk: mediatek: correct cpu clock name for MT8173 SoC
Correct cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72.
Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8173.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 96c292c3e440..deedeb3ea33b 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -533,7 +533,7 @@ static const char * const ca53_parents[] __initconst = { "univpll" }; -static const char * const ca57_parents[] __initconst = { +static const char * const ca72_parents[] __initconst = { "clk26m", "armca15pll", "mainpll", @@ -542,7 +542,7 @@ static const char * const ca57_parents[] __initconst = { static const struct mtk_composite cpu_muxes[] __initconst = { MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), - MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2), + MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), }; static const struct mtk_composite top_muxes[] __initconst = { |