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| author |   Marek Vasut <marex@denx.de> | 2022-09-27 01:45:01 +0200 |
|---|---|---|
| committer |   Rob Herring <robh@kernel.org> | 2022-09-29 17:29:04 -0500 |
| commit | 8ec747e5d585cc8efaf5ebc3caf5dd71af86eaaa (patch) | |
| tree | b308353ca458b3fae742a40ec282d21cc1547045 /drivers/fpga/fpga-bridge.c | |
| parent | dt-bindings: timer: Add power-domains for TI timer-dm on K3 (diff) | |
| download | wireguard-linux-8ec747e5d585cc8efaf5ebc3caf5dd71af86eaaa.tar.xz wireguard-linux-8ec747e5d585cc8efaf5ebc3caf5dd71af86eaaa.zip | |
dt-bindings: display: st,stm32-dsi: Handle data-lanes in DSI port node
Handle 'data-lanes' property of the DSI output endpoint, it is possible
to describe DSI link with 1 or 2 data lanes this way.
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20220926234501.583115-1-marex@denx.de
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions