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author | 2022-08-15 00:35:47 +0800 | |
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committer | 2022-08-31 21:05:38 +0200 | |
commit | ca08e46d4215e85eb3cef2481255431d98da56da (patch) | |
tree | f2bc31d92a8c08491df0720b76a4ea5b03318b91 /drivers/fpga/fpga-bridge.c | |
parent | cpufreq: amd_pstate: map desired perf into pstate scope for powersave governor (diff) | |
download | wireguard-linux-ca08e46d4215e85eb3cef2481255431d98da56da.tar.xz wireguard-linux-ca08e46d4215e85eb3cef2481255431d98da56da.zip |
cpufreq: amd-pstate: update pstate frequency transition delay time
Change the default transition latency to be 20ms that is more
reasonable transition delay for AMD processors in non-EPP driver mode.
Update transition delay time to 1ms, in the AMD CPU autonomous mode and
non-autonomous mode, CPPC firmware will decide frequency at 1ms timescale
based on the workload utilization.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions