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| author |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-07-27 12:39:54 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-07-27 12:39:54 +0200 |
| commit | eea2c51f81df9df5123c042f07c7c6c33bf5fabb (patch) | |
| tree | 03fbe44c178809b9b5174b599528068ca91f35ce /drivers/fpga | |
| parent | Revert "test_firmware: Test platform fw loading on non-EFI systems" (diff) | |
| parent | Linux 5.8-rc7 (diff) | |
| download | wireguard-linux-eea2c51f81df9df5123c042f07c7c6c33bf5fabb.tar.xz wireguard-linux-eea2c51f81df9df5123c042f07c7c6c33bf5fabb.zip | |
Merge 5.8-rc7 into driver-core-next
We want the driver core fixes in here as well.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/fpga')
| -rw-r--r-- | drivers/fpga/dfl-afu-main.c | 3 | ||||
| -rw-r--r-- | drivers/fpga/dfl-pci.c | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index b0c31789a909..3fa2c5992173 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -83,7 +83,8 @@ int __afu_port_disable(struct platform_device *pdev) * on this port and minimum soft reset pulse width has elapsed. * Driver polls port_soft_reset_ack to determine if reset done by HW. */ - if (readq_poll_timeout(base + PORT_HDR_CTRL, v, v & PORT_CTRL_SFTRST, + if (readq_poll_timeout(base + PORT_HDR_CTRL, v, + v & PORT_CTRL_SFTRST_ACK, RST_POLL_INVL, RST_POLL_TIMEOUT)) { dev_err(&pdev->dev, "timeout, fail to reset device\n"); return -ETIMEDOUT; diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index 538755062ab7..a78c409bf2c4 100644 --- a/drivers/fpga/dfl-pci.c +++ b/drivers/fpga/dfl-pci.c @@ -227,7 +227,6 @@ static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs) { struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); struct dfl_fpga_cdev *cdev = drvdata->cdev; - int ret = 0; if (!num_vfs) { /* @@ -239,6 +238,8 @@ static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs) dfl_fpga_cdev_config_ports_pf(cdev); } else { + int ret; + /* * before enable SRIOV, put released ports into VF access mode * first of all. |