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| author |   Anthony Koo <Anthony.Koo@amd.com> | 2019-02-15 14:19:30 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-03-19 15:04:03 -0500 |
| commit | 07d6a199219562834757ac72c28f3836b4e85694 (patch) | |
| tree | caba52fc93644be81e6293f2a689e17dfba01f9f /drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | |
| parent | drm/amd/display: Update plane tiling attributes for stream updates (diff) | |
| download | wireguard-linux-07d6a199219562834757ac72c28f3836b4e85694.tar.xz wireguard-linux-07d6a199219562834757ac72c28f3836b4e85694.zip | |
drm/amd/display: Fix soft hang issue when some DPCD data invalid
[Why]
AUX transaction returns success, but data has invalid lane count and rate
which when passed to VBIOS command table causes it to soft hang
[How]
Do some sanity checking and fail if the DPCD caps are invalid.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c')
0 files changed, 0 insertions, 0 deletions