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| author |   Alex Deucher <alexander.deucher@amd.com> | 2024-09-12 13:08:12 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-09-18 16:15:06 -0400 |
| commit | 797fb1533315571ff9e55e80154f48cd47f3dbe5 (patch) | |
| tree | c4714b2c8e4319e1836efab5b85fe2aac6098e9a /drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | |
| parent | drm/amdgpu: Fix selfring initialization sequence on soc24 (diff) | |
| download | wireguard-linux-797fb1533315571ff9e55e80154f48cd47f3dbe5.tar.xz wireguard-linux-797fb1533315571ff9e55e80154f48cd47f3dbe5.zip | |
drm/amdgpu/gfx9.4.3: set additional bits on MEC halt
Need to set the pipe reset and cache invalidation bits
on halt otherwise we can get stale state if the CP firmware
changes (e.g., on module unload and reload).
Tested-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_object.h')
0 files changed, 0 insertions, 0 deletions