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| author |   Hansen Dsouza <Hansen.Dsouza@amd.com> | 2024-10-15 17:33:15 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2024-10-28 16:32:29 -0400 |
| commit | 69f22c5b454f7a3d77f323ed96b4ad6ac7bbe378 (patch) | |
| tree | f6d638836058bf59007adccb1ec2dc04e5516dbd /drivers/gpu/drm/amd/display/amdgpu_dm | |
| parent | drm/amd/display: Optimize power up sequence for specific OLED (diff) | |
| download | wireguard-linux-69f22c5b454f7a3d77f323ed96b4ad6ac7bbe378.tar.xz wireguard-linux-69f22c5b454f7a3d77f323ed96b4ad6ac7bbe378.zip | |
drm/amd/display: Add a boot option to reduce phy ssc for HBR3
[Why]
Spread on DPREFCLK by 0.3 percent can have a negative effect on sink
when PHY SSC is also spread by 0.3 percent
[How]
Add boot option for DMU to lower PHY SSC
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm')
0 files changed, 0 insertions, 0 deletions