diff options
| author |   Alvin Lee <Alvin.Lee2@amd.com> | 2022-10-24 13:39:02 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-11-09 17:24:14 -0500 |
| commit | 00efc965a7b7990e63e3506e6d240e6271bd8571 (patch) | |
| tree | eab1bba696ad88e86d6fca73c0cfa6ed3171aa95 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | drm/amdgpu: workaround for TLB seq race (diff) | |
| download | wireguard-linux-00efc965a7b7990e63e3506e6d240e6271bd8571.tar.xz wireguard-linux-00efc965a7b7990e63e3506e6d240e6271bd8571.zip | |
drm/amd/display: Wait for VBLANK during pipe programming
[Description]
- Wait for vblank during front end programming
for global sync to ensure all double buffer
updates take.
- This prevents underflow in some cases.
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index f3334f513eb4..b465a83bde6f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1663,6 +1663,7 @@ static void dcn20_program_pipe( pipe_ctx->pipe_dlg_param.vupdate_width); if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) { + pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); } |