diff options
| author |   Wesley Chalmers <Wesley.Chalmers@amd.com> | 2022-11-03 22:29:31 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-07-07 13:51:48 -0400 |
| commit | 09c8cbedba5fa85f15ac91ed74848aceff69f8e5 (patch) | |
| tree | 15fbbd1ab0f154c3222c54964b9efb22edb4134d /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | drm/amdgpu: Fix error & warnings in gmc_v9_0.c (diff) | |
| download | wireguard-linux-09c8cbedba5fa85f15ac91ed74848aceff69f8e5.tar.xz wireguard-linux-09c8cbedba5fa85f15ac91ed74848aceff69f8e5.zip | |
drm/amd/display: Do not set drr on pipe commit
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
[HOW]
Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
optimized_required.
This change expects that Freesync requests are blocked when
optimized_required is true.
Fixes: 613a7956deb3 ("drm/amd/display: Add monitor specific edid quirk")
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 4492bc2392b6..dba7eab9a2c4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -2123,6 +2123,12 @@ void dcn20_optimize_bandwidth( if (hubbub->funcs->program_compbuf_size) hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); + if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { + dc_dmub_srv_p_state_delegate(dc, + true, context); + context->bw_ctx.bw.dcn.clk.p_state_change_support = true; + } + dc->clk_mgr->funcs->update_clocks( dc->clk_mgr, context, |