diff options
| author |   Melissa Wen <mwen@igalia.com> | 2023-05-23 21:15:16 -0100 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-06-30 13:12:15 -0400 |
| commit | 2dc84508f8c692d455b991a2feee85aa5d647568 (patch) | |
| tree | 7d1485c1e18c4b563fd3ec7e1b8e40bb790153f1 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | Revert "drm/amd/display: edp do not add non-edid timings" (diff) | |
| download | wireguard-linux-2dc84508f8c692d455b991a2feee85aa5d647568.tar.xz wireguard-linux-2dc84508f8c692d455b991a2feee85aa5d647568.zip | |
drm/amd/display: program DPP shaper and 3D LUT if updated
If shaper and 3D LUT data updates, lut_3d bit in update_flag is updated
and we need to call set_input_transfer_func to program DPP shaper and 3D
LUTs. Small cleanup of code style in the related if-condition.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index eaf9e9ccad2a..4c8aa3dfb959 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1764,8 +1764,9 @@ static void dcn20_program_pipe( hws->funcs.set_hdr_multiplier(pipe_ctx); if (pipe_ctx->update_flags.bits.enable || - pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || - pipe_ctx->plane_state->update_flags.bits.gamma_change) + pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || + pipe_ctx->plane_state->update_flags.bits.gamma_change || + pipe_ctx->plane_state->update_flags.bits.lut_3d) hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); /* dcn10_translate_regamma_to_hw_format takes 750us to finish |