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| author |   Michel Dänzer <mdaenzer@redhat.com> | 2023-05-22 15:08:22 +0200 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 10:54:44 -0400 |
| commit | 353491c48697df8a133bc468dc1b8ef65045254a (patch) | |
| tree | 1b1e5568c3eff8728faa3c58c37ca5f92c4af145 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | drm/amdgpu: Add a low priority scheduler for VRAM clearing (diff) | |
| download | wireguard-linux-353491c48697df8a133bc468dc1b8ef65045254a.tar.xz wireguard-linux-353491c48697df8a133bc468dc1b8ef65045254a.zip | |
Revert "drm/amd/display: Block optimize on consecutive FAMS enables"
This reverts commit 751e17147953bc30036b8fe0eaaf780b6951404c.
It depends on its parent commit, which we want to revert.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <mdaenzer@redhat.com>
[Hamza: fix a whitespace issue in dcn30_prepare_bandwidth()]
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index b0a13eb8318c..b56f799f10e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -2126,9 +2126,6 @@ void dcn20_optimize_bandwidth( dc_dmub_srv_p_state_delegate(dc, true, context); context->bw_ctx.bw.dcn.clk.p_state_change_support = true; - dc->clk_mgr->clks.fw_based_mclk_switching = true; - } else { - dc->clk_mgr->clks.fw_based_mclk_switching = false; } dc->clk_mgr->funcs->update_clocks( |