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authorEric Bernstein <eric.bernstein@amd.com>2022-04-01 13:49:45 -0400
committerAlex Deucher <alexander.deucher@amd.com>2022-07-05 16:11:00 -0400
commit64a30aaf0b0d9dcd52af526652937c1350a948dc (patch)
tree5215b5d6627953da73ad8c6775800f3422680fdd /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
parentdrm/amd/display: Prepare for new interfaces (diff)
downloadwireguard-linux-64a30aaf0b0d9dcd52af526652937c1350a948dc.tar.xz
wireguard-linux-64a30aaf0b0d9dcd52af526652937c1350a948dc.zip
drm/amd/display: Add function to set pixels per cycle
Add function to set pixels per cycle in DIG stream encoder Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 9f07c1b170c9..2286cc34e9cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2535,9 +2535,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
tg->funcs->set_early_control(tg, early_control);
- if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
- pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
- timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ? 2 : 1);
+ if (dc->hwseq->funcs.set_pixels_per_cycle)
+ dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);
/* enable audio only within mode set */
if (pipe_ctx->stream_res.audio != NULL) {