diff options
| author |   Wesley Chalmers <Wesley.Chalmers@amd.com> | 2023-02-28 13:48:00 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-04-26 22:27:26 -0400 |
| commit | ce560ac40272a5c8b5b68a9d63a75edd9e66aed2 (patch) | |
| tree | 365770256cab5ead4361ab17903b6ba90854b7b6 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | drm/amd/display: Do not set drr on pipe commit (diff) | |
| download | wireguard-linux-ce560ac40272a5c8b5b68a9d63a75edd9e66aed2.tar.xz wireguard-linux-ce560ac40272a5c8b5b68a9d63a75edd9e66aed2.zip | |
drm/amd/display: Block optimize on consecutive FAMS enables
[WHY]
It is possible to commit state multiple times in rapid succession with
FAMS enabled; if each of these commits were to set optimized_required,
then the user may see latency.
[HOW]
fw_based_mclk_switching is currently not used in dc->clk_mgr; use it
to track whether the current state has FAMS enabled;
if it has, then do not disable FAMS in prepare_bandwidth, and do not set
optimized_required.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 6ce10fd4bb1a..422fbf79da64 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -2117,6 +2117,9 @@ void dcn20_optimize_bandwidth( dc_dmub_srv_p_state_delegate(dc, true, context); context->bw_ctx.bw.dcn.clk.p_state_change_support = true; + dc->clk_mgr->clks.fw_based_mclk_switching = true; + } else { + dc->clk_mgr->clks.fw_based_mclk_switching = false; } dc->clk_mgr->funcs->update_clocks( |