aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
diff options
context:
space:
mode:
authorWesley Chalmers <Wesley.Chalmers@amd.com>2022-11-03 22:29:31 -0400
committerAlex Deucher <alexander.deucher@amd.com>2023-04-18 16:28:51 -0400
commite101bf95ea87ccc03ac2f48dfc0757c6364ff3c7 (patch)
tree5212acf588ff539adc4704e6cc4e9279887e2fe8 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
parentdrm/amd/display: Fix ABM pipe/backlight issues when change backlight (diff)
downloadwireguard-linux-e101bf95ea87ccc03ac2f48dfc0757c6364ff3c7.tar.xz
wireguard-linux-e101bf95ea87ccc03ac2f48dfc0757c6364ff3c7.zip
drm/amd/display: Do not set drr on pipe commit
[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. [HOW] Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets optimized_required. This change expects that Freesync requests are blocked when optimized_required is true. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 5403e9399a46..6ce10fd4bb1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2113,6 +2113,12 @@ void dcn20_optimize_bandwidth(
if (hubbub->funcs->program_compbuf_size)
hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+ dc_dmub_srv_p_state_delegate(dc,
+ true, context);
+ context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
+ }
+
dc->clk_mgr->funcs->update_clocks(
dc->clk_mgr,
context,