diff options
| author |   Noah Abradjian <noah.abradjian@amd.com> | 2019-12-17 15:49:14 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-01-16 14:13:53 -0500 |
| commit | c1e3417558beda21fd41ed870ca16b36a69188d5 (patch) | |
| tree | 5172d8d42dcbff9cb2e2da91f28644aa6f3625e9 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h | |
| parent | drm/amd/display: DMCUB FW Changes to support PSR (diff) | |
| download | wireguard-linux-c1e3417558beda21fd41ed870ca16b36a69188d5.tar.xz wireguard-linux-c1e3417558beda21fd41ed870ca16b36a69188d5.zip | |
drm/amd/display: Indirect reg read macro with shift and mask
[Why]
Recent double buffering changes for dcn2 use IX_REG_READ.
However, this macro returns the full register value, with the need to
manually shift and mask it to retrieve field data.
[How]
Create new IX_REG_GET macro that handles shift and mask.
Use this for double buffering reads instead of IX_REG_READ.
Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h index 950e6f9cd23e..c78fd5123497 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h @@ -140,7 +140,6 @@ SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ - SF(MPC_OCSC_TEST_DEBUG_DATA, MPC_OCSC_TEST_DEBUG_DATA, mask_sh),\ SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\ SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ @@ -189,7 +188,12 @@ * OCSC Mode: [1..0] */ #define MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX 1 -#define MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE_MASK 0x3 + +#define MPC_DEBUG_REG_LIST_SH_DCN20 \ + .MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0 + +#define MPC_DEBUG_REG_LIST_MASK_DCN20 \ + .MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0x3 #define MPC_REG_FIELD_LIST_DCN2_0(type) \ MPC_REG_FIELD_LIST(type)\ @@ -198,7 +202,7 @@ type MPCC_TOP_GAIN;\ type MPCC_BOT_GAIN_INSIDE;\ type MPCC_BOT_GAIN_OUTSIDE;\ - type MPC_OCSC_TEST_DEBUG_DATA;\ + type MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE;\ type MPC_OCSC_TEST_DEBUG_INDEX;\ type MPC_OCSC_MODE;\ type MPC_OCSC_C11_A;\ |