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| author |   Ahmad Othman <ahmad.Othman@amd.com> | 2021-10-05 21:04:03 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-10-28 14:26:14 -0400 |
| commit | ffd89aa968d9046ab5fb9f7cdb7f8d3c383a15c1 (patch) | |
| tree | 8da97c3b5d644d833336aac47d7bcd7182340107 /drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | |
| parent | drm/amd/display: dc_link_set_psr_allow_active refactoring (diff) | |
| download | wireguard-linux-ffd89aa968d9046ab5fb9f7cdb7f8d3c383a15c1.tar.xz wireguard-linux-ffd89aa968d9046ab5fb9f7cdb7f8d3c383a15c1.zip | |
drm/amd/display: Add support for USB4 on C20 PHY for DCN3.1
[Why]
Created new fields that matches new B0 structs On DCN31 the mapping of
DIO output to PHY differs from A0 to B0 boards with new PHY C20 & this
new mapping needed to be handled.
[How]
Mapped new structure based on new structs Added logic for mapping over
A0 and B0 boards Hooked all new structs together.
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Ahmad Othman <Ahmad.Othman@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c')
0 files changed, 0 insertions, 0 deletions