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| author |   Dillon Varone <Dillon.Varone@amd.com> | 2022-09-09 12:49:55 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-09-29 09:41:45 -0400 |
| commit | 1e939ea1bf4917095575fe4ff1a42578ff234605 (patch) | |
| tree | 9ad939bdcf38d3ec0882f6feb79a1fa34a5297cb /drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | |
| parent | drm/amd/display: polling vid stream status in hpo dp blank (diff) | |
| download | wireguard-linux-1e939ea1bf4917095575fe4ff1a42578ff234605.tar.xz wireguard-linux-1e939ea1bf4917095575fe4ff1a42578ff234605.zip | |
drm/amd/display: Fix various dynamic ODM transitions on DCN32
[Why&How]
Several transitions were fixed that will allow Dynamic ODM and MPO
transitions to be supported on DCN32.
1) Due to resource limitations, in certain scenarios that require an MPO
plane to be split, the features cannot be combined with the current
policy. This is due to unsafe transitions being required (OPP instance
per MPCC being switched on active pipe is not supported by DCN), to
support the split plane with ODM active as it moves across the viewport.
Dynamic ODM will now be disabled when MPO is required.
2) When exiting MPO and re-entering ODM, DC assigns an inactive pipe for
the next ODM pipe, which under previous power gating policy would result
in programming a gated DSC HW block. New policy dynamically
gates/un-gates DSC blocks when Dynamic ODM is active to support
transitions on DCN32 only.
3) Entry and exit from 3 plane MPO and Dynamic ODM requires a minimal
transition so that all pipes which require their MPCC OPP instance to
be changed have a full frame to be disabled before reprogramming. To
solve this, the Dynamic ODM policy now utilizes minimal state
transitions when entering or exiting 3 plane scenarios.
4) Various fixes to DCN32 pipe merge/split algorithm to support Dynamic
ODM and MPO transitions.
In summary, this commit fixes various transitions to support ODM->MPO
and MPO->ODM.
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index d35b0618c3c1..d04b68dad413 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -84,6 +84,7 @@ struct hw_sequencer_funcs { struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); void (*update_pending_status)(struct pipe_ctx *pipe_ctx); void (*power_down)(struct dc *dc); + void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); /* Pipe Lock Related */ void (*pipe_control_lock)(struct dc *dc, |