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authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>2021-01-19 14:10:21 -0500
committerAlex Deucher <alexander.deucher@amd.com>2021-01-21 09:54:26 -0500
commit7fc75382ec687e43efa0232c8b9b5bffa6b57dcd (patch)
tree8b464e6ba27276042ca44254c8b5112816c58c7b /drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
parentdrm/amd/display: Enable programing of MALL watermarks (diff)
downloadwireguard-linux-7fc75382ec687e43efa0232c8b9b5bffa6b57dcd.tar.xz
wireguard-linux-7fc75382ec687e43efa0232c8b9b5bffa6b57dcd.zip
drm/amd/display: Dynamic cursor cache size for MALL eligibility check
[Why] Currently we use the maximum possible cursor cache size when deciding if we should attempt to enable MALL, but this prevents us from enabling the feature for certain key use cases. [How] - consider cursor bpp when calculating if the cursor fits Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 48378beb71c0..0586ab2ffd6a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -218,7 +218,8 @@ struct hw_sequencer_funcs {
/* Idle Optimization Related */
bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
- bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane);
+ bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane,
+ struct dc_cursor_attributes *cursor_attr);
bool (*is_abm_supported)(struct dc *dc,
struct dc_state *context, struct dc_stream_state *stream);