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authorTaimur Hassan <syed.hassan@amd.com>2020-09-10 10:13:42 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-09-22 12:28:56 -0400
commit99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1 (patch)
treeefdd809c796cd7c0c2cbda913f3c71ebd3a055fa /drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
parentdrm/amd/display: Implement PSR wait for enable/disable (diff)
downloadwireguard-linux-99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1.tar.xz
wireguard-linux-99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1.zip
drm/amd/display: Check for flip pending before locking pipes.
[Why] When running a game/benchmark with v-sync disabled, disabling a plane (which is v-sync) can cause an underflow. This is due to flips that are pending before pipe locking being applied after locks are released and pipes have been re-arranged or disconnected. This can potentially apply a flip on the incorrect pipe. [How] Check that any pending flips are cleared before locking any pipes to ensure flips are applied on the correct pipes. Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 64c1be818b0e..f48ee24d42f9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -67,7 +67,7 @@ struct hw_sequencer_funcs {
int num_planes, struct dc_state *context);
void (*program_front_end_for_ctx)(struct dc *dc,
struct dc_state *context);
- bool (*disconnect_pipes)(struct dc *dc,
+ void (*disconnect_pipes)(struct dc *dc,
struct dc_state *context);
void (*wait_for_pending_cleared)(struct dc *dc,
struct dc_state *context);