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authorJake Wang <haonan.wang2@amd.com>2021-08-05 14:43:41 -0400
committerAlex Deucher <alexander.deucher@amd.com>2021-08-16 16:14:12 -0400
commitf586fea897609a61020a4438ee45542ad848abe9 (patch)
tree5dc8e53abeacc4f8fab7fd6ce49ff2f812f0f464 /drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
parentdrm/amd/display: Use vblank control events for PSR enable/disable (diff)
downloadwireguard-linux-f586fea897609a61020a4438ee45542ad848abe9.tar.xz
wireguard-linux-f586fea897609a61020a4438ee45542ad848abe9.zip
drm/amd/display: Ensure DCN save after VM setup
[Why] DM initializes VM context after DMCUB initialization. This results in loss of DCN_VM_CONTEXT registers after z10. [How] Notify DMCUB when VM setup is complete, and have DMCUB save init registers. v2: squash in CONFIG_DRM_AMD_DC_DCN3_1 fix Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 5ab008e62b82..ad5f2adcc40d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -237,6 +237,7 @@ struct hw_sequencer_funcs {
int width, int height, int offset);
void (*z10_restore)(struct dc *dc);
+ void (*z10_save_init)(struct dc *dc);
void (*update_visual_confirm_color)(struct dc *dc,
struct pipe_ctx *pipe_ctx,