diff options
| author |   Hansen Dsouza <Hansen.Dsouza@amd.com> | 2025-01-15 14:21:24 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2025-02-12 21:02:59 -0500 |
| commit | 871f65a59f3cca534e54ab0efe9d976cdd05ac9a (patch) | |
| tree | 5f8cc2c120ff2eac42e2ce5e6bbd322860b14e94 /drivers/gpu/drm/amd/display/dmub/src | |
| parent | drm/amd/display: Ammend DCPG IP control sequences to align with HW guidance (diff) | |
| download | wireguard-linux-871f65a59f3cca534e54ab0efe9d976cdd05ac9a.tar.xz wireguard-linux-871f65a59f3cca534e54ab0efe9d976cdd05ac9a.zip | |
drm/amd/display: Add boot option to reduce PHY SSC for HBR3
[Why]
Spread on DPREFCLK by 0.3 percent can have a negative effect on sink
when PHY SSC is also spread by 0.3 percent
[How]
Add boot option for DMU to lower PHY SSC
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/src')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c index d9f31b191c69..3d0bba602b53 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c @@ -371,6 +371,7 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu boot_options.bits.usb4_cm_version = params->usb4_cm_version; boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; boot_options.bits.power_optimization = params->power_optimization; + boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0; |