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| author |   Lewis Huang <Lewis.Huang@amd.com> | 2021-09-29 16:32:15 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-10-28 14:26:13 -0400 |
| commit | cafea7728ca66a16dc45724b8bc13da89f703ee4 (patch) | |
| tree | 805a045451c5a04d2425ba4af0e9ef7d46e7dd4d /drivers/gpu/drm/amd/display/modules/freesync | |
| parent | drm/amdgpu/pm: look up current_level for asics without pm callback (diff) | |
| download | wireguard-linux-cafea7728ca66a16dc45724b8bc13da89f703ee4.tar.xz wireguard-linux-cafea7728ca66a16dc45724b8bc13da89f703ee4.zip | |
drm/amd/display: Align bw context with hw config when system resume
[Why]
When the vbios config and driver config are different, if we update
clock to lower before call program_timing and program_pixel_clk, garbage
appear.
[How]
Align bw context with hw config when system resume
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync')
0 files changed, 0 insertions, 0 deletions