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authorAlvin Lee <alvin.lee2@amd.com>2024-04-17 18:44:16 -0400
committerAlex Deucher <alexander.deucher@amd.com>2024-04-30 09:56:21 -0400
commit3351c608f373bc76dcfa773723c2d1f7c5b5c55e (patch)
treea297ba0325175786954042e1058926dc05da5ebe /drivers/gpu/drm/amd/display
parentdrm/amd/display: Revert "dc: Keep VBios pixel rate div setting util next mode set" (diff)
downloadwireguard-linux-3351c608f373bc76dcfa773723c2d1f7c5b5c55e.tar.xz
wireguard-linux-3351c608f373bc76dcfa773723c2d1f7c5b5c55e.zip
drm/amd/display: Only program P-State force if pipe config changed
[Description] Today for MED update type we do not call update clocks. However, for FPO the assumption is that update clocks should be called to disable P-State switch before any HW programming since FPO in FW and driver are not synchronized. This causes an issue where on a MED update, an FPO P-State switch could be taking place, then driver forces P-State disallow in the below code and prevents FPO from completing the sequence. In this case we add a check to avoid re-programming (and thus re-setting) the P-State force register by only reprogramming if the pipe was not previously Subvp or FPO. The assumption is that the P-State force register should be programmed correctly the first time SubVP / FPO was enabled, so there's no need to update / reset it if the pipe config has never exited SubVP / FPO. Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display')
-rw-r--r--drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index b8e884368dc6..4d75ce5561e4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -614,10 +614,26 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)
*/
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
struct hubp *hubp = pipe->plane_res.hubp;
+ /* Today for MED update type we do not call update clocks. However, for FPO
+ * the assumption is that update clocks should be called to disable P-State
+ * switch before any HW programming since FPO in FW and driver are not
+ * synchronized. This causes an issue where on a MED update, an FPO P-State
+ * switch could be taking place, then driver forces P-State disallow in the below
+ * code and prevents FPO from completing the sequence. In this case we add a check
+ * to avoid re-programming (and thus re-setting) the P-State force register by
+ * only reprogramming if the pipe was not previously Subvp or FPO. The assumption
+ * is that the P-State force register should be programmed correctly the first
+ * time SubVP / FPO was enabled, so there's no need to update / reset it if the
+ * pipe config has never exited SubVP / FPO.
+ */
if (pipe->stream && (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||
- pipe->stream->fpo_in_use)) {
+ pipe->stream->fpo_in_use) &&
+ (!old_pipe->stream ||
+ (dc_state_get_pipe_subvp_type(context, old_pipe) != SUBVP_MAIN &&
+ !old_pipe->stream->fpo_in_use))) {
if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)