diff options
| author |   Victor Zhao <Victor.Zhao@amd.com> | 2022-06-21 16:59:44 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-08-16 18:14:31 -0400 |
| commit | bfaced6ee77484d8b9c6baf86a8e9406f80108c5 (patch) | |
| tree | aa16a3b0b5dbc3425bfb4c270b488ee026edcf9e /drivers/gpu/drm/amd/include | |
| parent | drm/amdgpu: add debugfs amdgpu_reset_level (diff) | |
| download | wireguard-linux-bfaced6ee77484d8b9c6baf86a8e9406f80108c5.tar.xz wireguard-linux-bfaced6ee77484d8b9c6baf86a8e9406f80108c5.zip | |
drm/amdgpu: save and restore gc hub regs
Save and restore gfxhub regs as they will be reset during mode 2
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h index f21554a1c86c..594bffce93a9 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h @@ -3129,6 +3129,8 @@ #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15cc #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define mmGCVM_DEBUG 0x15cd +#define mmGCVM_DEBUG_BASE_IDX 0 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15ce #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15cf @@ -3151,6 +3153,8 @@ #define mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 #define mmGCVM_L2_CACHE_PARITY_CNTL 0x15d8 #define mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define mmGCVM_L2_IH_LOG_CNTL 0x15d9 +#define mmGCVM_L2_IH_LOG_CNTL_BASE_IDX 0 #define mmGCVM_L2_CNTL5 0x15dc #define mmGCVM_L2_CNTL5_BASE_IDX 0 #define mmGCVM_L2_GCR_CNTL 0x15dd |