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| author |   Prike Liang <Prike.Liang@amd.com> | 2019-09-25 14:11:41 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-10-03 09:11:04 -0500 |
| commit | 2cf8d416d32b1e9425c923e7c3444cdd7c09f18f (patch) | |
| tree | 9588da771f9a0c9a3bc719cd215bf90ed89e7809 /drivers/gpu/drm/amd/powerplay/renoir_ppt.c | |
| parent | drm/amd/powerplay: implement interface set_power_profile_mode() (v2) (diff) | |
| download | wireguard-linux-2cf8d416d32b1e9425c923e7c3444cdd7c09f18f.tar.xz wireguard-linux-2cf8d416d32b1e9425c923e7c3444cdd7c09f18f.zip | |
drm/amd/powerplay: implement the interface for setting sclk/uclk profile_peak level
Add the interface for setting sclk and uclk peak frequency.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/renoir_ppt.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c index 3785b7fd3d66..c11f8d74b7f8 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c @@ -510,6 +510,45 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u return 0; } +static int renoir_set_peak_clock_by_device(struct smu_context *smu) +{ + int ret = 0; + uint32_t sclk_freq = 0, uclk_freq = 0; + + ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq); + if (ret) + return ret; + + ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq); + if (ret) + return ret; + + ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq); + if (ret) + return ret; + + ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq); + if (ret) + return ret; + + return ret; +} + +static int renoir_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) +{ + int ret = 0; + + switch (level) { + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: + ret = renoir_set_peak_clock_by_device(smu); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} static const struct pptable_funcs renoir_ppt_funcs = { .get_smu_msg_index = renoir_get_smu_msg_index, @@ -526,6 +565,7 @@ static const struct pptable_funcs renoir_ppt_funcs = { .get_profiling_clk_mask = renoir_get_profiling_clk_mask, .force_clk_levels = renoir_force_clk_levels, .set_power_profile_mode = renoir_set_power_profile_mode, + .set_performance_level = renoir_set_performance_level, }; void renoir_set_ppt_funcs(struct smu_context *smu) |