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| author |   Prike Liang <Prike.Liang@amd.com> | 2020-03-04 10:36:21 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-03-05 00:32:16 -0500 |
| commit | 781345f9ef03cbdc7720897b6b2aa7dfe7ec69ac (patch) | |
| tree | 424abeffeb6a6f2da7d3e1831ac710182a2f3a98 /drivers/gpu/drm/amd/powerplay/renoir_ppt.c | |
| parent | drm/amd/powerplay: fix pre-check condition for setting clock range (diff) | |
| download | wireguard-linux-781345f9ef03cbdc7720897b6b2aa7dfe7ec69ac.tar.xz wireguard-linux-781345f9ef03cbdc7720897b6b2aa7dfe7ec69ac.zip | |
drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case
When hit COMBINATIONAL_BYPASS the mclk will be bypass and can export
fclk frequency to user usage.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/renoir_ppt.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c index cca4820afaa6..653faadaafb3 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c @@ -111,8 +111,8 @@ static struct smu_12_0_cmn2aisc_mapping renoir_clk_map[SMU_CLK_COUNT] = { CLK_MAP(GFXCLK, CLOCK_GFXCLK), CLK_MAP(SCLK, CLOCK_GFXCLK), CLK_MAP(SOCCLK, CLOCK_SOCCLK), - CLK_MAP(UCLK, CLOCK_UMCCLK), - CLK_MAP(MCLK, CLOCK_UMCCLK), + CLK_MAP(UCLK, CLOCK_FCLK), + CLK_MAP(MCLK, CLOCK_FCLK), }; static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = { @@ -280,7 +280,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, break; case SMU_MCLK: count = NUM_MEMCLK_DPM_LEVELS; - cur_value = metrics.ClockFrequency[CLOCK_UMCCLK]; + cur_value = metrics.ClockFrequency[CLOCK_FCLK]; break; case SMU_DCEFCLK: count = NUM_DCFCLK_DPM_LEVELS; |