diff options
| author |   Victor Lu <victorchengchi.lu@amd.com> | 2025-02-13 18:41:26 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2025-03-07 12:52:29 -0500 |
| commit | 3646cc65e2747ff112d7de1a05a2e756414b771e (patch) | |
| tree | 78ee4de087f8557aa32e763763eca02d65194c43 /drivers/gpu/drm/amd | |
| parent | drm/amdgpu: Fix core reset sequence for JPEG5_0_1 (diff) | |
| download | wireguard-linux-3646cc65e2747ff112d7de1a05a2e756414b771e.tar.xz wireguard-linux-3646cc65e2747ff112d7de1a05a2e756414b771e.zip | |
drm/amdgpu: Do not write to GRBM_CNTL if Aldebaran SRIOV
Aldebaran SRIOV VF does not have write permissions to GRBM_CTNL.
This access can be skipped to avoid a dmesg warning.
v2: Use GC IP version check instead of asic check
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index f7938d318f26..1f0f03108a82 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2637,7 +2637,10 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) u32 tmp; int i; - WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); + if (!amdgpu_sriov_vf(adev) || + amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2)) { + WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); + } gfx_v9_0_tiling_mode_table_init(adev); |