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author | 2015-01-22 17:01:24 +0000 | |
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committer | 2015-02-13 23:28:11 +0100 | |
commit | 766436004bde5855dcf9975bff2bcd606bd908ab (patch) | |
tree | 0e302f627485cd05e09f1a209b6021a48470cc80 /drivers/gpu/drm/drm_ioctl.c | |
parent | drm/i915/trace: Fix offsets for 64b (diff) | |
download | wireguard-linux-766436004bde5855dcf9975bff2bcd606bd908ab.tar.xz wireguard-linux-766436004bde5855dcf9975bff2bcd606bd908ab.zip |
drm/i915: Rename to GEN8_LEGACY_PDPES
In gen8, 32b PPGTT has always had one "pdp" (it doesn't actually have
one, but it resembles having one). The #define was confusing as is, and
using "PDPE" is a much better description.
sed -i 's/GEN8_LEGACY_PDPS/GEN8_LEGACY_PDPES/' drivers/gpu/drm/i915/*.[ch]
It also matches the x86 pagetable terminology:
PTE = Page Table Entry - pagetable level 1 page
PDE = Page Directory Entry - pagetable level 2 page
PDPE = Page Directory Pointer Entry - pagetable level 3 page
And in the near future (for 48b addressing):
PML4E = Page Map Level 4 Entry
v2: Expanded information about Page Directory/Table nomenclature.
Cc: Daniel Vetter <daniel@ffwll.ch>
CC: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Michel Thierry <michel.thierry@intel.com> (v2)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/drm_ioctl.c')
0 files changed, 0 insertions, 0 deletions