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| author |   Matt Roper <matthew.d.roper@intel.com> | 2019-09-10 08:42:52 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2019-09-10 20:37:29 -0700 |
| commit | 0c1279b58fc7de230d47bb0dc21b7a08417dee96 (patch) | |
| tree | ce0dd23444c5f42267a9a2cdcca8fd75d723b45b /drivers/gpu/drm/i915/display/intel_atomic.c | |
| parent | drm/i915: Enhance cdclk sanitization (diff) | |
| download | wireguard-linux-0c1279b58fc7de230d47bb0dc21b7a08417dee96.tar.xz wireguard-linux-0c1279b58fc7de230d47bb0dc21b7a08417dee96.zip | |
drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk
The BXT and CNL functions were already basically identical, whereas
ICL's function tried to do its own sanitization rather than calling
bxt_sanitize_cdclk.
This should actually fix a bug in our ICL initialization where it would
consider the /2 CD2X divider invalid and force an unnecessary
sanitization (we now have valid clock frequencies that use this
divider).
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190910154252.30503-9-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_atomic.c')
0 files changed, 0 insertions, 0 deletions