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| author |   Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2020-06-08 09:55:52 +0300 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2020-06-08 12:03:15 +0300 |
| commit | 46d53e271cea5740a19384c4365217c9cb86bdfc (patch) | |
| tree | bb0a8fa3acc3d959addc8dff0b0786715233a692 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | drm/i915/psr: Program default IO buffer Wake and Fast Wake (diff) | |
| download | wireguard-linux-46d53e271cea5740a19384c4365217c9cb86bdfc.tar.xz wireguard-linux-46d53e271cea5740a19384c4365217c9cb86bdfc.zip | |
Revert "drm/i915: Remove unneeded hack now for CDCLK"
This reverts commit 82ea174dc5425d4e85e25d0c4ba961a2e494392a.
Unfortunately according to our recent findings there is still some
unidentified factor, requiring CDCLK to be set higher - otherwise we
still get underruns on some multipipe configurations, despite CDCLK
being set according to BSpec formula. So getting again back into debug
mode to indentify the cause, meanwhile setting CDCLK=Pixel rate back in
order to remove regression in 10% of the cases due to FIFO underruns.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200608065552.21728-1-stanislav.lisovskiy@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions