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| author |   José Roberto de Souza <jose.souza@intel.com> | 2020-10-19 10:56:09 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2020-10-19 17:25:55 -0700 |
| commit | a21906ead6a59419613f803460ca900f2560b1e1 (patch) | |
| tree | 9c5d2f345e062e5845c9d698eb63f52f344f7438 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | drm/i915/display: Program DBUF_CTL tracker state service (diff) | |
| download | wireguard-linux-a21906ead6a59419613f803460ca900f2560b1e1.tar.xz wireguard-linux-a21906ead6a59419613f803460ca900f2560b1e1.zip | |
drm/i915/display/fbc: Implement WA 22010751166
Underruns happens when plane height + y offset is not a modulo of 4
when FBC is enabled. It happens when scanline is at vactive - 10 but
that is not feasible to do from the software side so here completely
disabling FBC when height + y offset matches to avoid visual glitches.
Specification says that it only affects TGL display C stepping and
newer but to simply the check and as TGL is already in final costumers
hands, pre-production display stepping A and B was also included.
BSpec: 52887 ICL
BSpec: 52888 EHL/JSL
BSpec: 52890/55378 TGL
BSpec: 53508 DG1
BSpec: 53273 RKL
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201019175609.28715-1-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions