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author | 2020-06-03 14:15:22 -0700 | |
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committer | 2020-06-04 09:35:23 -0700 | |
commit | cd0a89527d06f19e9e6eb7efce81c629c4b76b43 (patch) | |
tree | 033e586b8ebbabbe635721647d91c028ce584d60 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
parent | drm/i915/rkl: provide port/phy mapping for vbt (diff) | |
download | wireguard-linux-cd0a89527d06f19e9e6eb7efce81c629c4b76b43.tar.xz wireguard-linux-cd0a89527d06f19e9e6eb7efce81c629c4b76b43.zip |
drm/i915/rkl: Add DDC pin mapping
The pin mapping for the final two outputs varies according to which PCH
is present on the platform: with TGP the pins are remapped into the TC
range, whereas with CMP they stay in the traditional combo output range.
Bspec: 49181
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200603211529.3005059-9-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions