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| author |   José Roberto de Souza <jose.souza@intel.com> | 2021-04-21 15:02:23 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-04-26 13:08:04 -0700 |
| commit | d5b5f63cc5b0e7cf9b16b694215bc43fb6b71441 (patch) | |
| tree | cb7511256a1b29327aafc5c6ce53c84f786d74c2 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | drm/i915: Simplify CCS and UV plane alignment handling (diff) | |
| download | wireguard-linux-d5b5f63cc5b0e7cf9b16b694215bc43fb6b71441.tar.xz wireguard-linux-d5b5f63cc5b0e7cf9b16b694215bc43fb6b71441.zip | |
drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec
DP_PSR_EN_CFG bit 5 aka "Selective Update Region Scan Line Capture
Indication" in eDP spec has a ambiguous name, so renaming to better
match specification.
While at it, replacing bit shit by BIT() macro and adding the version
some registers were added to eDP specification.
Cc: <dri-devel@lists.freedesktop.org>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421220224.200729-1-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions