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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-12-02 15:44:10 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-12-08 21:33:02 +0200 |
| commit | 944bda740fc953d37d8a8a5506193c6031ecd2f9 (patch) | |
| tree | 29135f20a7c1f15cf6958f9e4b18a4175ae46c2b /drivers/gpu/drm/i915/display/intel_panel.c | |
| parent | drm/i915/vrr: Make registers latch in a consitent place on icl/tgl (diff) | |
| download | wireguard-linux-944bda740fc953d37d8a8a5506193c6031ecd2f9.tar.xz wireguard-linux-944bda740fc953d37d8a8a5506193c6031ecd2f9.zip | |
drm/i915/vrr: Fix guardband/vblank exit length calculation for adl+
We are miscalculating both the guardband value, and the resulting
vblank exit length on adl+. This means that our start of vblank
(double buffered register latch point) is incorrect, and we also
think that it's not where it actually is (hence vblank evasion/etc.
may not work properly). Fix up the calculations to match the real
hardware behaviour (as reverse engineered by intel_display_poller).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221202134412.21943-3-ville.syrjala@linux.intel.com
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_panel.c')
0 files changed, 0 insertions, 0 deletions