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| author |   Jouni Högander <jouni.hogander@intel.com> | 2023-12-18 19:50:03 +0200 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2024-01-09 15:39:59 +0200 |
| commit | 467e4e061c44ff79cdd2c6b5cbc42842caf189f1 (patch) | |
| tree | 3d5cb8998dafb43264c0e55f091a7476788c9578 /drivers/gpu/drm/i915/display/intel_psr.h | |
| parent | drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transport (diff) | |
| download | wireguard-linux-467e4e061c44ff79cdd2c6b5cbc42842caf189f1.tar.xz wireguard-linux-467e4e061c44ff79cdd2c6b5cbc42842caf189f1.zip | |
drm/i915/psr: Enable psr2 early transport as possible
Check source and sink support for psr2 early transport and enable
it if not disabled by debug flag.
Bspec: 68934
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231218175004.52875-7-jouni.hogander@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_psr.h')
0 files changed, 0 insertions, 0 deletions