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| author |   Matt Roper <matthew.d.roper@intel.com> | 2022-03-10 22:28:35 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-03-11 08:18:27 -0800 |
| commit | 239bbb2fe927ed762bfe6307ba6a2e2d94e739da (patch) | |
| tree | eda1786119342288854ad72d38ee58e30b04bbcb /drivers/gpu/drm/i915/gt/intel_engine_types.h | |
| parent | drm/i915/gem: add missing boundary check in vm_access (diff) | |
| download | wireguard-linux-239bbb2fe927ed762bfe6307ba6a2e2d94e739da.tar.xz wireguard-linux-239bbb2fe927ed762bfe6307ba6a2e2d94e739da.zip | |
drm/i915/gt: Remove GEN12_SFC_DONE_MAX from register defs header
We shouldn't really be keeping track of how many SFC_DONE registers
our platforms can have, but rather how many SFC hardware units there can
be (each SFC unit will have one corresponding SFC_DONE register). So
drop the stray GEN12_SFC_DONE_MAX definition we had in the register
definition file and replace it with an I915_MAX_SFC that follows the
pattern we use for other hardware units. Note that our hardware has a
2:1:1 ratio of VD:VE:SFC, and as far as we know that pattern should
carry forward to future platforms, so we'll define it as #VCS/2.
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220311062835.163744-1-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_engine_types.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 4fbf45a74ec0..85c00025a2ff 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -96,6 +96,7 @@ struct i915_ctx_workarounds { #define I915_MAX_VCS 8 #define I915_MAX_VECS 4 +#define I915_MAX_SFC (I915_MAX_VCS / 2) #define I915_MAX_CCS 4 #define I915_MAX_RCS 1 |