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| author |   Matt Roper <matthew.d.roper@intel.com> | 2022-03-03 14:34:34 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-03-04 08:02:15 -0800 |
| commit | f9576e36c6b4f070d0b95fd968c1a73fec5a193b (patch) | |
| tree | cdc137780e4d9fb94f3667f4e930263ee8d13a24 /drivers/gpu/drm/i915/gt/intel_engine_types.h | |
| parent | drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs (diff) | |
| download | wireguard-linux-f9576e36c6b4f070d0b95fd968c1a73fec5a193b.tar.xz wireguard-linux-f9576e36c6b4f070d0b95fd968c1a73fec5a193b.zip | |
drm/i915/xehp: Support platforms with CCS engines but no RCS
In the past we've always assumed that an RCS engine is present on every
platform. However now that we have compute engines there may be
platforms that have CCS engines but no RCS, or platforms that are
designed to have both, but have the RCS engine fused off.
Various engine-centric initialization that only needs to be done a
single time for the group of RCS+CCS engines can't rely on being setup
with the RCS now; instead we add a I915_ENGINE_FIRST_RENDER_COMPUTE flag
that will be assigned to a single engine in the group; whichever engine
has this flag will be responsible for some of the general setup
(RCU_MODE programming, initialization of certain workarounds, etc.).
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220303223435.2793124-1-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_engine_types.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 19ff8758e34d..4fbf45a74ec0 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -97,6 +97,7 @@ struct i915_ctx_workarounds { #define I915_MAX_VCS 8 #define I915_MAX_VECS 4 #define I915_MAX_CCS 4 +#define I915_MAX_RCS 1 /* * Engine IDs definitions. @@ -526,6 +527,7 @@ struct intel_engine_cs { #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8) #define I915_ENGINE_HAS_RCS_REG_STATE BIT(9) #define I915_ENGINE_HAS_EU_PRIORITY BIT(10) +#define I915_ENGINE_FIRST_RENDER_COMPUTE BIT(11) unsigned int flags; /* |