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| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-09-10 09:02:08 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-09-10 11:04:17 +0100 |
| commit | fa9a09f15065650d97e3b1336d11e4ad9672b759 (patch) | |
| tree | ca73d43fd3e60c089457c4786423546966ecce5c /drivers/gpu/drm/i915/gt/intel_lrc_reg.h | |
| parent | drm/i915: include GTT page-size info in error state (diff) | |
| download | wireguard-linux-fa9a09f15065650d97e3b1336d11e4ad9672b759.tar.xz wireguard-linux-fa9a09f15065650d97e3b1336d11e4ad9672b759.zip | |
drm/i915/execlists: Clear STOP_RING bit on reset
During reset, we try to ensure no forward progress of the CS prior to
the reset by setting the STOP_RING bit in RING_MI_MODE. Since gen9, this
register is context saved and do we end up in the odd situation where we
save the STOP_RING bit and so try to stop the engine again immediately
upon resume. This is quite unexpected and causes us to complain about an
early CS completion event!
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111514
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190910080208.4223-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_lrc_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h index 68caf8541866..7e773e74a3fe 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h @@ -39,6 +39,8 @@ #define CTX_R_PWR_CLK_STATE 0x42 #define CTX_END 0x44 +#define GEN9_CTX_RING_MI_MODE 0x54 + /* GEN12+ Reg State Context */ #define GEN12_CTX_BB_PER_CTX_PTR 0x12 #define GEN12_CTX_LRI_HEADER_3 0x41 |