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| author |   Suraj Kandpal <suraj.kandpal@intel.com> | 2023-07-20 16:16:24 +0530 |
|---|---|---|
| committer |   Uma Shankar <uma.shankar@intel.com> | 2023-07-26 10:28:13 +0530 |
| commit | 4948738e296c75de57e0c4a8e8ead1ff2c03fe00 (patch) | |
| tree | e6e5b6194fbb13f8e9eb60eeb332372a1560799e /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Simplify expression &to_i915(dev)->drm (diff) | |
| download | wireguard-linux-4948738e296c75de57e0c4a8e8ead1ff2c03fe00.tar.xz wireguard-linux-4948738e296c75de57e0c4a8e8ead1ff2c03fe00.zip | |
drm/i915/hotplug: Reduce SHPD_FILTER to 250us
On TGP, the RTC (always running) was reduced from 3MHz to 32KHz.
As a result of this change, when HPD active going low pulse or HPD IRQ
is presented and the refclk (19.2MHz) is not toggling already toggling,
there is a 60 to 90us synchronization delay which effectively reduces
the duration of the IRQ pulse to less than the programmed 500us filter
value and the hot plug interrupt is NOT registered.
Solution was to Reduce SHPD_FILTER to 250us for ADL and above.
This solution was derived when the below patch was floated.
[1]https://patchwork.freedesktop.org/patch/532187
and after some internal discussion Ville's suggestion made sense.
Bspec: 68970
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230720104624.3063544-1-suraj.kandpal@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7a4f462e8b70..4f94a0367cb9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4917,6 +4917,7 @@ #define SHPD_FILTER_CNT _MMIO(0xc4038) #define SHPD_FILTER_CNT_500_ADJ 0x001D9 +#define SHPD_FILTER_CNT_250 0x000F8 #define _PCH_DPLL_A 0xc6014 #define _PCH_DPLL_B 0xc6018 |