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authorDaniel Vetter <daniel.vetter@ffwll.ch>2023-04-06 16:31:32 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2023-04-06 16:31:33 +0200
commit4d877b1a6e855d1c8685fa0e27ad7a521b31b6ca (patch)
tree24c7e6084e77ed638f8134d49564e7c5cca84431 /drivers/gpu/drm/i915/i915_reg.h
parentMerge tag 'drm/tegra/for-6.4-rc1' of https://gitlab.freedesktop.org/drm/tegra into drm-next (diff)
parentdrm/i915/wakeref: fix kernel-doc comment (diff)
downloadwireguard-linux-4d877b1a6e855d1c8685fa0e27ad7a521b31b6ca.tar.xz
wireguard-linux-4d877b1a6e855d1c8685fa0e27ad7a521b31b6ca.zip
Merge tag 'drm-intel-next-2023-04-06' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- Fix DPT+shmem combo and add i915.enable_dpt modparam (Ville) - i915.enable_sagv module parameter (Ville) - Correction to QGV related register addresses (Vinod) - IPS debugfs per-crtc and new file for false_color (Ville) - More clean-up and reorganization of Display code (Jani) - DP DSC related fixes and improvements (Stanislav, Ankit, Suraj, Swati) - Make utility pin asserts more accurate (Ville) - Meteor Lake enabling (Daniele) - High refresh rate PSR fixes (Jouni) - Cursor and Plane chicken register fixes (Ville) - Align the ADL-P TypeC sequences with hardware specification (Imre) - Documentation build fixes and improvements to catch bugs earlier (Lee, Jani) - PL1 power limit hwmon entry changed to use 0 as disabled state (Ashutosh) - DP aux sync fix and improvements (Ville) - DP MST fixes and w/a (Stanislav) - Limit PXP drm-errors or warning on firmware API failures (Alan) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZC7RR3Laet8ywHRo@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1243
1 files changed, 22 insertions, 1221 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8dac20b0e7a7..736a8dcf777b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1067,39 +1067,6 @@
#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
-#define _PIPEA_MBUS_DBOX_CTL 0x7003C
-#define _PIPEB_MBUS_DBOX_CTL 0x7103C
-#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
- _PIPEB_MBUS_DBOX_CTL)
-#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */
-#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)
-#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */
-#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)
-#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
-#define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
-#define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
-#define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)
-#define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)
-#define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
-#define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
-#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
-#define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)
-#define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
-#define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
-
-#define MBUS_UBOX_CTL _MMIO(0x4503C)
-#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
-#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
-
-#define MBUS_CTL _MMIO(0x4438C)
-#define MBUS_JOIN REG_BIT(31)
-#define MBUS_HASHING_MODE_MASK REG_BIT(30)
-#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
-#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
-#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
-#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
-#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
-
/* Make render/texture TLB fetches lower priorty than associated data
* fetches. This is not turned on by default
*/
@@ -1407,7 +1374,8 @@
#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
#define IPS_CTL _MMIO(0x43408)
-#define IPS_ENABLE (1 << 31)
+#define IPS_ENABLE REG_BIT(31)
+#define IPS_FALSE_COLOR REG_BIT(4)
#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
#define FBC_REND_NUKE REG_BIT(2)
@@ -2013,11 +1981,6 @@
#define PIPESRC(pipe) _MMIO_TRANS2((pipe), _PIPEASRC)
#define TRANS_MULT(trans) _MMIO_TRANS2((trans), _TRANS_MULT_A)
-#define TRANS_EXITLINE(trans) _MMIO_TRANS2((trans), _TRANS_EXITLINE_A)
-#define EXITLINE_ENABLE REG_BIT(31)
-#define EXITLINE_MASK REG_GENMASK(12, 0)
-#define EXITLINE_SHIFT 0
-
/* VRR registers */
#define _TRANS_VRR_CTL_A 0x60420
#define _TRANS_VRR_CTL_B 0x61420
@@ -2111,205 +2074,6 @@
#define TRANS_PUSH_EN REG_BIT(31)
#define TRANS_PUSH_SEND REG_BIT(30)
-/*
- * HSW+ eDP PSR registers
- *
- * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
- * instance of it
- */
-#define _SRD_CTL_A 0x60800
-#define _SRD_CTL_EDP 0x6f800
-#define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A)
-#define EDP_PSR_ENABLE (1 << 31)
-#define BDW_PSR_SINGLE_FRAME (1 << 30)
-#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
-#define EDP_PSR_LINK_STANDBY (1 << 27)
-#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
-#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
-#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
-#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
-#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
-#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
-#define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
-#define EDP_PSR_TP1_TP2_SEL (0 << 11)
-#define EDP_PSR_TP1_TP3_SEL (1 << 11)
-#define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */
-#define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
-#define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
-#define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
-#define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
-#define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */
-#define EDP_PSR_TP1_TIME_500us (0 << 4)
-#define EDP_PSR_TP1_TIME_100us (1 << 4)
-#define EDP_PSR_TP1_TIME_2500us (2 << 4)
-#define EDP_PSR_TP1_TIME_0us (3 << 4)
-#define EDP_PSR_IDLE_FRAME_SHIFT 0
-
-/*
- * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
- * to transcoder and bits defined for each one as if using no shift (i.e. as if
- * it was for TRANSCODER_EDP)
- */
-#define EDP_PSR_IMR _MMIO(0x64834)
-#define EDP_PSR_IIR _MMIO(0x64838)
-#define _PSR_IMR_A 0x60814
-#define _PSR_IIR_A 0x60818
-#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A)
-#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
-#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
- 0 : ((trans) - TRANSCODER_A + 1) * 8)
-#define TGL_PSR_MASK REG_GENMASK(2, 0)
-#define TGL_PSR_ERROR REG_BIT(2)
-#define TGL_PSR_POST_EXIT REG_BIT(1)
-#define TGL_PSR_PRE_ENTRY REG_BIT(0)
-#define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \
- _EDP_PSR_TRANS_SHIFT(trans))
-#define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \
- _EDP_PSR_TRANS_SHIFT(trans))
-#define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \
- _EDP_PSR_TRANS_SHIFT(trans))
-#define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \
- _EDP_PSR_TRANS_SHIFT(trans))
-
-#define _SRD_AUX_DATA_A 0x60814
-#define _SRD_AUX_DATA_EDP 0x6f814
-#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */
-
-#define _SRD_STATUS_A 0x60840
-#define _SRD_STATUS_EDP 0x6f840
-#define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A)
-#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
-#define EDP_PSR_STATUS_STATE_SHIFT 29
-#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
-#define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
-#define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
-#define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
-#define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
-#define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
-#define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
-#define EDP_PSR_STATUS_LINK_MASK (3 << 26)
-#define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
-#define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
-#define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
-#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
-#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
-#define EDP_PSR_STATUS_COUNT_SHIFT 16
-#define EDP_PSR_STATUS_COUNT_MASK 0xf
-#define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
-#define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
-#define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
-#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
-#define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
-#define EDP_PSR_STATUS_IDLE_MASK 0xf
-
-#define _SRD_PERF_CNT_A 0x60844
-#define _SRD_PERF_CNT_EDP 0x6f844
-#define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A)
-#define EDP_PSR_PERF_CNT_MASK 0xffffff
-
-/* PSR_MASK on SKL+ */
-#define _SRD_DEBUG_A 0x60860
-#define _SRD_DEBUG_EDP 0x6f860
-#define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A)
-#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
-#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
-#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
-#define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
-#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
-#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
-
-#define _PSR2_CTL_A 0x60900
-#define _PSR2_CTL_EDP 0x6f900
-#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
-#define EDP_PSR2_ENABLE (1 << 31)
-#define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
-#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
-#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
-#define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
-#define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */
-#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
-#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
-#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8
-#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
-#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13)
-#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
-#define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13
-#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
-#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13)
-#define EDP_PSR2_FAST_WAKE_MAX_LINES 8
-#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
-#define EDP_PSR2_FAST_WAKE_MASK (3 << 11)
-#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5
-#define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10
-#define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
-#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10)
-#define EDP_PSR2_TP2_TIME_500us (0 << 8)
-#define EDP_PSR2_TP2_TIME_100us (1 << 8)
-#define EDP_PSR2_TP2_TIME_2500us (2 << 8)
-#define EDP_PSR2_TP2_TIME_50us (3 << 8)
-#define EDP_PSR2_TP2_TIME_MASK (3 << 8)
-#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
-#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
-#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
-#define EDP_PSR2_IDLE_FRAME_MASK 0xf
-#define EDP_PSR2_IDLE_FRAME_SHIFT 0
-
-#define _PSR_EVENT_TRANS_A 0x60848
-#define _PSR_EVENT_TRANS_B 0x61848
-#define _PSR_EVENT_TRANS_C 0x62848
-#define _PSR_EVENT_TRANS_D 0x63848
-#define _PSR_EVENT_TRANS_EDP 0x6f848
-#define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
-#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
-#define PSR_EVENT_PSR2_DISABLED (1 << 16)
-#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
-#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
-#define PSR_EVENT_GRAPHICS_RESET (1 << 12)
-#define PSR_EVENT_PCH_INTERRUPT (1 << 11)
-#define PSR_EVENT_MEMORY_UP (1 << 10)
-#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
-#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
-#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
-#define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
-#define PSR_EVENT_HDCP_ENABLE (1 << 4)
-#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
-#define PSR_EVENT_VBI_ENABLE (1 << 2)
-#define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
-#define PSR_EVENT_PSR_DISABLE (1 << 0)
-
-#define _PSR2_STATUS_A 0x60940
-#define _PSR2_STATUS_EDP 0x6f940
-#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
-#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
-#define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
-
-#define _PSR2_SU_STATUS_A 0x60914
-#define _PSR2_SU_STATUS_EDP 0x6f914
-#define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4)
-#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
-#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
-#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
-#define PSR2_SU_STATUS_FRAMES 8
-
-#define _PSR2_MAN_TRK_CTL_A 0x60910
-#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
-#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
-#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
-#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
-#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
-#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
-#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
-#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
-#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
-#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
-#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
-#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
-#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
-#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
-#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
-#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
-#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
-
/* VGA port control */
#define ADPA _MMIO(0x61100)
#define PCH_ADPA _MMIO(0xe1100)
@@ -2566,73 +2330,6 @@
#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
-/* Panel power sequencing */
-#define PPS_BASE 0x61200
-#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
-#define PCH_PPS_BASE 0xC7200
-
-#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \
- PPS_BASE + (reg) + \
- (pps_idx) * 0x100)
-
-#define _PP_STATUS 0x61200
-#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
-#define PP_ON REG_BIT(31)
-/*
- * Indicates that all dependencies of the panel are on:
- *
- * - PLL enabled
- * - pipe enabled
- * - LVDS/DVOB/DVOC on
- */
-#define PP_READY REG_BIT(30)
-#define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
-#define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
-#define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
-#define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
-#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
-#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
-#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
-#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
-#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
-#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
-#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
-#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
-#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
-#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
-#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
-
-#define _PP_CONTROL 0x61204
-#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
-#define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
-#define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
-#define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
-#define EDP_FORCE_VDD REG_BIT(3)
-#define EDP_BLC_ENABLE REG_BIT(2)
-#define PANEL_POWER_RESET REG_BIT(1)
-#define PANEL_POWER_ON REG_BIT(0)
-
-#define _PP_ON_DELAYS 0x61208
-#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
-#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
-#define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
-#define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
-#define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
-#define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
-#define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
-#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
-#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
-
-#define _PP_OFF_DELAYS 0x6120C
-#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
-#define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
-#define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
-
-#define _PP_DIVISOR 0x61210
-#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
-#define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
-#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
-
/* Panel fitting */
#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
#define PFIT_ENABLE (1 << 31)
@@ -2670,485 +2367,6 @@
#define PCH_GTC_CTL _MMIO(0xe7000)
#define PCH_GTC_ENABLE (1 << 31)
-/* TV port control */
-#define TV_CTL _MMIO(0x68000)
-/* Enables the TV encoder */
-# define TV_ENC_ENABLE (1 << 31)
-/* Sources the TV encoder input from pipe B instead of A. */
-# define TV_ENC_PIPE_SEL_SHIFT 30
-# define TV_ENC_PIPE_SEL_MASK (1 << 30)
-# define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
-/* Outputs composite video (DAC A only) */
-# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
-/* Outputs SVideo video (DAC B/C) */
-# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
-/* Outputs Component video (DAC A/B/C) */
-# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
-/* Outputs Composite and SVideo (DAC A/B/C) */
-# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
-# define TV_TRILEVEL_SYNC (1 << 21)
-/* Enables slow sync generation (945GM only) */
-# define TV_SLOW_SYNC (1 << 20)
-/* Selects 4x oversampling for 480i and 576p */
-# define TV_OVERSAMPLE_4X (0 << 18)
-/* Selects 2x oversampling for 720p and 1080i */
-# define TV_OVERSAMPLE_2X (1 << 18)
-/* Selects no oversampling for 1080p */
-# define TV_OVERSAMPLE_NONE (2 << 18)
-/* Selects 8x oversampling */
-# define TV_OVERSAMPLE_8X (3 << 18)
-# define TV_OVERSAMPLE_MASK (3 << 18)
-/* Selects progressive mode rather than interlaced */
-# define TV_PROGRESSIVE (1 << 17)
-/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
-# define TV_PAL_BURST (1 << 16)
-/* Field for setting delay of Y compared to C */
-# define TV_YC_SKEW_MASK (7 << 12)
-/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
-# define TV_ENC_SDP_FIX (1 << 11)
-/*
- * Enables a fix for the 915GM only.
- *
- * Not sure what it does.
- */
-# define TV_ENC_C0_FIX (1 << 10)
-/* Bits that must be preserved by software */
-# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
-# define TV_FUSE_STATE_MASK (3 << 4)
-/* Read-only state that reports all features enabled */
-# define TV_FUSE_STATE_ENABLED (0 << 4)
-/* Read-only state that reports that Macrovision is disabled in hardware*/
-# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
-/* Read-only state that reports that TV-out is disabled in hardware. */
-# define TV_FUSE_STATE_DISABLED (2 << 4)
-/* Normal operation */
-# define TV_TEST_MODE_NORMAL (0 << 0)
-/* Encoder test pattern 1 - combo pattern */
-# define TV_TEST_MODE_PATTERN_1 (1 << 0)
-/* Encoder test pattern 2 - full screen vertical 75% color bars */
-# define TV_TEST_MODE_PATTERN_2 (2 << 0)
-/* Encoder test pattern 3 - full screen horizontal 75% color bars */
-# define TV_TEST_MODE_PATTERN_3 (3 << 0)
-/* Encoder test pattern 4 - random noise */
-# define TV_TEST_MODE_PATTERN_4 (4 << 0)
-/* Encoder test pattern 5 - linear color ramps */
-# define TV_TEST_MODE_PATTERN_5 (5 << 0)
-/*
- * This test mode forces the DACs to 50% of full output.
- *
- * This is used for load detection in combination with TVDAC_SENSE_MASK
- */
-# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
-# define TV_TEST_MODE_MASK (7 << 0)
-
-#define TV_DAC _MMIO(0x68004)
-# define TV_DAC_SAVE 0x00ffff00
-/*
- * Reports that DAC state change logic has reported change (RO).
- *
- * This gets cleared when TV_DAC_STATE_EN is cleared
-*/
-# define TVDAC_STATE_CHG (1 << 31)
-# define TVDAC_SENSE_MASK (7 << 28)
-/* Reports that DAC A voltage is above the detect threshold */
-# define TVDAC_A_SENSE (1 << 30)
-/* Reports that DAC B voltage is above the detect threshold */
-# define TVDAC_B_SENSE (1 << 29)
-/* Reports that DAC C voltage is above the detect threshold */
-# define TVDAC_C_SENSE (1 << 28)
-/*
- * Enables DAC state detection logic, for load-based TV detection.
- *
- * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
- * to off, for load detection to work.
- */
-# define TVDAC_STATE_CHG_EN (1 << 27)
-/* Sets the DAC A sense value to high */
-# define TVDAC_A_SENSE_CTL (1 << 26)
-/* Sets the DAC B sense value to high */
-# define TVDAC_B_SENSE_CTL (1 << 25)
-/* Sets the DAC C sense value to high */
-# define TVDAC_C_SENSE_CTL (1 << 24)
-/* Overrides the ENC_ENABLE and DAC voltage levels */
-# define DAC_CTL_OVERRIDE (1 << 7)
-/* Sets the slew rate. Must be preserved in software */
-# define ENC_TVDAC_SLEW_FAST (1 << 6)
-# define DAC_A_1_3_V (0 << 4)
-# define DAC_A_1_1_V (1 << 4)
-# define DAC_A_0_7_V (2 << 4)
-# define DAC_A_MASK (3 << 4)
-# define DAC_B_1_3_V (0 << 2)
-# define DAC_B_1_1_V (1 << 2)
-# define DAC_B_0_7_V (2 << 2)
-# define DAC_B_MASK (3 << 2)
-# define DAC_C_1_3_V (0 << 0)
-# define DAC_C_1_1_V (1 << 0)
-# define DAC_C_0_7_V (2 << 0)
-# define DAC_C_MASK (3 << 0)
-
-/*
- * CSC coefficients are stored in a floating point format with 9 bits of
- * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
- * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
- * -1 (0x3) being the only legal negative value.
- */
-#define TV_CSC_Y _MMIO(0x68010)
-# define TV_RY_MASK 0x07ff0000
-# define TV_RY_SHIFT 16
-# define TV_GY_MASK 0x00000fff
-# define TV_GY_SHIFT 0
-
-#define TV_CSC_Y2 _MMIO(0x68014)
-# define TV_BY_MASK 0x07ff0000
-# define TV_BY_SHIFT 16
-/*
- * Y attenuation for component video.
- *
- * Stored in 1.9 fixed point.
- */
-# define TV_AY_MASK 0x000003ff
-# define TV_AY_SHIFT 0
-
-#define TV_CSC_U _MMIO(0x68018)
-# define TV_RU_MASK 0x07ff0000
-# define TV_RU_SHIFT 16
-# define TV_GU_MASK 0x000007ff
-# define TV_GU_SHIFT 0
-
-#define TV_CSC_U2 _MMIO(0x6801c)
-# define TV_BU_MASK 0x07ff0000
-# define TV_BU_SHIFT 16
-/*
- * U attenuation for component video.
- *
- * Stored in 1.9 fixed point.
- */
-# define TV_AU_MASK 0x000003ff
-# define TV_AU_SHIFT 0
-
-#define TV_CSC_V _MMIO(0x68020)
-# define TV_RV_MASK 0x0fff0000
-# define TV_RV_SHIFT 16
-# define TV_GV_MASK 0x000007ff
-# define TV_GV_SHIFT 0
-
-#define TV_CSC_V2 _MMIO(0x68024)
-# define TV_BV_MASK 0x07ff0000
-# define TV_BV_SHIFT 16
-/*
- * V attenuation for component video.
- *
- * Stored in 1.9 fixed point.
- */
-# define TV_AV_MASK 0x000007ff
-# define TV_AV_SHIFT 0
-
-#define TV_CLR_KNOBS _MMIO(0x68028)
-/* 2s-complement brightness adjustment */
-# define TV_BRIGHTNESS_MASK 0xff000000
-# define TV_BRIGHTNESS_SHIFT 24
-/* Contrast adjustment, as a 2.6 unsigned floating point number */
-# define TV_CONTRAST_MASK 0x00ff0000
-# define TV_CONTRAST_SHIFT 16
-/* Saturation adjustment, as a 2.6 unsigned floating point number */
-# define TV_SATURATION_MASK 0x0000ff00
-# define TV_SATURATION_SHIFT 8
-/* Hue adjustment, as an integer phase angle in degrees */
-# define TV_HUE_MASK 0x000000ff
-# define TV_HUE_SHIFT 0
-
-#define TV_CLR_LEVEL _MMIO(0x6802c)
-/* Controls the DAC level for black */
-# define TV_BLACK_LEVEL_MASK 0x01ff0000
-# define TV_BLACK_LEVEL_SHIFT 16
-/* Controls the DAC level for blanking */
-# define TV_BLANK_LEVEL_MASK 0x000001ff
-# define TV_BLANK_LEVEL_SHIFT 0
-
-#define TV_H_CTL_1 _MMIO(0x68030)
-/* Number of pixels in the hsync. */
-# define TV_HSYNC_END_MASK 0x1fff0000
-# define TV_HSYNC_END_SHIFT 16
-/* Total number of pixels minus one in the line (display and blanking). */
-# define TV_HTOTAL_MASK 0x00001fff
-# define TV_HTOTAL_SHIFT 0
-
-#define TV_H_CTL_2 _MMIO(0x68034)
-/* Enables the colorburst (needed for non-component color) */
-# define TV_BURST_ENA (1 << 31)
-/* Offset of the colorburst from the start of hsync, in pixels minus one. */
-# define TV_HBURST_START_SHIFT 16
-# define TV_HBURST_START_MASK 0x1fff0000
-/* Length of the colorburst */
-# define TV_HBURST_LEN_SHIFT 0
-# define TV_HBURST_LEN_MASK 0x0001fff
-
-#define TV_H_CTL_3 _MMIO(0x68038)
-/* End of hblank, measured in pixels minus one from start of hsync */
-# define TV_HBLANK_END_SHIFT 16
-# define TV_HBLANK_END_MASK 0x1fff0000
-/* Start of hblank, measured in pixels minus one from start of hsync */
-# define TV_HBLANK_START_SHIFT 0
-# define TV_HBLANK_START_MASK 0x0001fff
-
-#define TV_V_CTL_1 _MMIO(0x6803c)
-/* XXX */
-# define TV_NBR_END_SHIFT 16
-# define TV_NBR_END_MASK 0x07ff0000
-/* XXX */
-# define TV_VI_END_F1_SHIFT 8
-# define TV_VI_END_F1_MASK 0x00003f00
-/* XXX */
-# define TV_VI_END_F2_SHIFT 0
-# define TV_VI_END_F2_MASK 0x0000003f
-
-#define TV_V_CTL_2 _MMIO(0x68040)
-/* Length of vsync, in half lines */
-# define TV_VSYNC_LEN_MASK 0x07ff0000
-# define TV_VSYNC_LEN_SHIFT 16
-/* Offset of the start of vsync in field 1, measured in one less than the
- * number of half lines.
- */
-# define TV_VSYNC_START_F1_MASK 0x00007f00
-# define TV_VSYNC_START_F1_SHIFT 8
-/*
- * Offset of the start of vsync in field 2, measured in one less than the
- * number of half lines.
- */
-# define TV_VSYNC_START_F2_MASK 0x0000007f
-# define TV_VSYNC_START_F2_SHIFT 0
-
-#define TV_V_CTL_3 _MMIO(0x68044)
-/* Enables generation of the equalization signal */
-# define TV_EQUAL_ENA (1 << 31)
-/* Length of vsync, in half lines */
-# define TV_VEQ_LEN_MASK 0x007f0000
-# define TV_VEQ_LEN_SHIFT 16
-/* Offset of the start of equalization in field 1, measured in one less than
- * the number of half lines.
- */
-# define TV_VEQ_START_F1_MASK 0x0007f00
-# define TV_VEQ_START_F1_SHIFT 8
-/*
- * Offset of the start of equalization in field 2, measured in one less than
- * the number of half lines.
- */
-# define TV_VEQ_START_F2_MASK 0x000007f
-# define TV_VEQ_START_F2_SHIFT 0
-
-#define TV_V_CTL_4 _MMIO(0x68048)
-/*
- * Offset to start of vertical colorburst, measured in one less than the
- * number of lines from vertical start.
- */
-# define TV_VBURST_START_F1_MASK 0x003f0000
-# define TV_VBURST_START_F1_SHIFT 16
-/*
- * Offset to the end of vertical colorburst, measured in one less than the
- * number of lines from the start of NBR.
- */
-# define TV_VBURST_END_F1_MASK 0x000000ff
-# define TV_VBURST_END_F1_SHIFT 0
-
-#define TV_V_CTL_5 _MMIO(0x6804c)
-/*
- * Offset to start of vertical colorburst, measured in one less than the
- * number of lines from vertical start.
- */
-# define TV_VBURST_START_F2_MASK 0x003f0000
-# define TV_VBURST_START_F2_SHIFT 16
-/*
- * Offset to the end of vertical colorburst, measured in one less than the
- * number of lines from the start of NBR.
- */
-# define TV_VBURST_END_F2_MASK 0x000000ff
-# define TV_VBURST_END_F2_SHIFT 0
-
-#define TV_V_CTL_6 _MMIO(0x68050)
-/*
- * Offset to start of vertical colorburst, measured in one less than the
- * number of lines from vertical start.
- */
-# define TV_VBURST_START_F3_MASK 0x003f0000
-# define TV_VBURST_START_F3_SHIFT 16
-/*
- * Offset to the end of vertical colorburst, measured in one less than the
- * number of lines from the start of NBR.
- */
-# define TV_VBURST_END_F3_MASK 0x000000ff
-# define TV_VBURST_END_F3_SHIFT 0
-
-#define TV_V_CTL_7 _MMIO(0x68054)
-/*
- * Offset to start of vertical colorburst, measured in one less than the
- * number of lines from vertical start.
- */
-# define TV_VBURST_START_F4_MASK 0x003f0000
-# define TV_VBURST_START_F4_SHIFT 16
-/*
- * Offset to the end of vertical colorburst, measured in one less than the
- * number of lines from the start of NBR.
- */
-# define TV_VBURST_END_F4_MASK 0x000000ff
-# define TV_VBURST_END_F4_SHIFT 0
-
-#define TV_SC_CTL_1 _MMIO(0x68060)
-/* Turns on the first subcarrier phase generation DDA */
-# define TV_SC_DDA1_EN (1 << 31)
-/* Turns on the first subcarrier phase generation DDA */
-# define TV_SC_DDA2_EN (1 << 30)
-/* Turns on the first subcarrier phase generation DDA */
-# define TV_SC_DDA3_EN (1 << 29)
-/* Sets the subcarrier DDA to reset frequency every other field */
-# define TV_SC_RESET_EVERY_2 (0 << 24)
-/* Sets the subcarrier DDA to reset frequency every fourth field */
-# define TV_SC_RESET_EVERY_4 (1 << 24)
-/* Sets the subcarrier DDA to reset frequency every eighth field */
-# define TV_SC_RESET_EVERY_8 (2 << 24)
-/* Sets the subcarrier DDA to never reset the frequency */
-# define TV_SC_RESET_NEVER (3 << 24)
-/* Sets the peak amplitude of the colorburst.*/
-# define TV_BURST_LEVEL_MASK 0x00ff0000
-# define TV_BURST_LEVEL_SHIFT 16
-/* Sets the increment of the first subcarrier phase generation DDA */
-# define TV_SCDDA1_INC_MASK 0x00000fff
-# define TV_SCDDA1_INC_SHIFT 0
-
-#define TV_SC_CTL_2 _MMIO(0x68064)
-/* Sets the rollover for the second subcarrier phase generation DDA */
-# define TV_SCDDA2_SIZE_MASK 0x7fff0000
-# define TV_SCDDA2_SIZE_SHIFT 16
-/* Sets the increent of the second subcarrier phase generation DDA */
-# define TV_SCDDA2_INC_MASK 0x00007fff
-# define TV_SCDDA2_INC_SHIFT 0
-
-#define TV_SC_CTL_3 _MMIO(0x68068)
-/* Sets the rollover for the third subcarrier phase generation DDA */
-# define TV_SCDDA3_SIZE_MASK 0x7fff0000
-# define TV_SCDDA3_SIZE_SHIFT 16
-/* Sets the increent of the third subcarrier phase generation DDA */
-# define TV_SCDDA3_INC_MASK 0x00007fff
-# define TV_SCDDA3_INC_SHIFT 0
-
-#define TV_WIN_POS _MMIO(0x68070)
-/* X coordinate of the display from the start of horizontal active */
-# define TV_XPOS_MASK 0x1fff0000
-# define TV_XPOS_SHIFT 16
-/* Y coordinate of the display from the start of vertical active (NBR) */
-# define TV_YPOS_MASK 0x00000fff
-# define TV_YPOS_SHIFT 0
-
-#define TV_WIN_SIZE _MMIO(0x68074)
-/* Horizontal size of the display window, measured in pixels*/
-# define TV_XSIZE_MASK 0x1fff0000
-# define TV_XSIZE_SHIFT 16
-/*
- * Vertical size of the display window, measured in pixels.
- *
- * Must be even for interlaced modes.
- */
-# define TV_YSIZE_MASK 0x00000fff
-# define TV_YSIZE_SHIFT 0
-
-#define TV_FILTER_CTL_1 _MMIO(0x68080)
-/*
- * Enables automatic scaling calculation.
- *
- * If set, the rest of the registers are ignored, and the calculated values can
- * be read back from the register.
- */
-# define TV_AUTO_SCALE (1 << 31)
-/*
- * Disables the vertical filter.
- *
- * This is required on modes more than 1024 pixels wide */
-# define TV_V_FILTER_BYPASS (1 << 29)
-/* Enables adaptive vertical filtering */
-# define TV_VADAPT (1 << 28)
-# define TV_VADAPT_MODE_MASK (3 << 26)
-/* Selects the least adaptive vertical filtering mode */
-# define TV_VADAPT_MODE_LEAST (0 << 26)
-/* Selects the moderately adaptive vertical filtering mode */
-# define TV_VADAPT_MODE_MODERATE (1 << 26)
-/* Selects the most adaptive vertical filtering mode */
-# define TV_VADAPT_MODE_MOST (3 << 26)
-/*
- * Sets the horizontal scaling factor.
- *
- * This should be the fractional part of the horizontal scaling factor divided
- * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
- *
- * (src width - 1) / ((oversample * dest width) - 1)
- */
-# define TV_HSCALE_FRAC_MASK 0x00003fff
-# define TV_HSCALE_FRAC_SHIFT 0
-
-#define TV_FILTER_CTL_2 _MMIO(0x68084)
-/*
- * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
- *
- * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
- */
-# define TV_VSCALE_INT_MASK 0x00038000
-# define TV_VSCALE_INT_SHIFT 15
-/*
- * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
- *
- * \sa TV_VSCALE_INT_MASK
- */
-# define TV_VSCALE_FRAC_MASK 0x00007fff
-# define TV_VSCALE_FRAC_SHIFT 0
-
-#define TV_FILTER_CTL_3 _MMIO(0x68088)
-/*
- * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
- *
- * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
- *
- * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
- */
-# define TV_VSCALE_IP_INT_MASK 0x00038000
-# define TV_VSCALE_IP_INT_SHIFT 15
-/*
- * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
- *
- * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
- *
- * \sa TV_VSCALE_IP_INT_MASK
- */
-# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
-# define TV_VSCALE_IP_FRAC_SHIFT 0
-
-#define TV_CC_CONTROL _MMIO(0x68090)
-# define TV_CC_ENABLE (1 << 31)
-/*
- * Specifies which field to send the CC data in.
- *
- * CC data is usually sent in field 0.
- */
-# define TV_CC_FID_MASK (1 << 27)
-# define TV_CC_FID_SHIFT 27
-/* Sets the horizontal position of the CC data. Usually 135. */
-# define TV_CC_HOFF_MASK 0x03ff0000
-# define TV_CC_HOFF_SHIFT 16
-/* Sets the vertical position of the CC data. Usually 21 */
-# define TV_CC_LINE_MASK 0x0000003f
-# define TV_CC_LINE_SHIFT 0
-
-#define TV_CC_DATA _MMIO(0x68094)
-# define TV_CC_RDY (1 << 31)
-/* Second word of CC data to be transmitted. */
-# define TV_CC_DATA_2_MASK 0x007f0000
-# define TV_CC_DATA_2_SHIFT 16
-/* First word of CC data to be transmitted. */
-# define TV_CC_DATA_1_MASK 0x0000007f
-# define TV_CC_DATA_1_SHIFT 0
-
-#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
-#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
-#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
-#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
-
/* Display Port */
#define DP_A _MMIO(0x64000) /* eDP */
#define DP_B _MMIO(0x64100)
@@ -3242,79 +2460,6 @@
/* A fantasy */
#define DP_DETECTED (1 << 2)
-/* The aux channel provides a way to talk to the
- * signal sink for DDC etc. Max packet size supported
- * is 20 bytes in each direction, hence the 5 fixed
- * data registers
- */
-#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
-#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
-
-#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
-#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
-
-#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
-#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
-
-#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
-#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
-#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
-#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
-
-#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
- _DPA_AUX_CH_CTL, \
- _DPB_AUX_CH_CTL, \
- 0, /* port/aux_ch C is non-existent */ \
- _XELPDP_USBC1_AUX_CH_CTL, \
- _XELPDP_USBC2_AUX_CH_CTL, \
- _XELPDP_USBC3_AUX_CH_CTL, \
- _XELPDP_USBC4_AUX_CH_CTL))
-
-#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
-#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
-#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
-#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
-
-#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
- _DPA_AUX_CH_DATA1, \
- _DPB_AUX_CH_DATA1, \
- 0, /* port/aux_ch C is non-existent */ \
- _XELPDP_USBC1_AUX_CH_DATA1, \
- _XELPDP_USBC2_AUX_CH_DATA1, \
- _XELPDP_USBC3_AUX_CH_DATA1, \
- _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
-
-#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
-#define DP_AUX_CH_CTL_DONE (1 << 30)
-#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
-#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
-#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
-#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
-#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
-#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
-#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
-#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19)
-#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18)
-#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
-#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
-#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
-#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
-#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
-#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
-#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
-#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
-#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
-#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
-#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
-#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
-#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
-#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
-#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
-#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
-
/*
* Computing GMCH M and N values for the Display Port link
*
@@ -3819,66 +2964,6 @@
#define I965_CURSOR_MAX_WM 32
#define I965_CURSOR_DFT_WM 8
-/* Watermark register definitions for SKL */
-#define _CUR_WM_A_0 0x70140
-#define _CUR_WM_B_0 0x71140
-#define _CUR_WM_SAGV_A 0x70158
-#define _CUR_WM_SAGV_B 0x71158
-#define _CUR_WM_SAGV_TRANS_A 0x7015C
-#define _CUR_WM_SAGV_TRANS_B 0x7115C
-#define _CUR_WM_TRANS_A 0x70168
-#define _CUR_WM_TRANS_B 0x71168
-#define _PLANE_WM_1_A_0 0x70240
-#define _PLANE_WM_1_B_0 0x71240
-#define _PLANE_WM_2_A_0 0x70340
-#define _PLANE_WM_2_B_0 0x71340
-#define _PLANE_WM_SAGV_1_A 0x70258
-#define _PLANE_WM_SAGV_1_B 0x71258
-#define _PLANE_WM_SAGV_2_A 0x70358
-#define _PLANE_WM_SAGV_2_B 0x71358
-#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
-#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
-#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
-#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
-#define _PLANE_WM_TRANS_1_A 0x70268
-#define _PLANE_WM_TRANS_1_B 0x71268
-#define _PLANE_WM_TRANS_2_A 0x70368
-#define _PLANE_WM_TRANS_2_B 0x71368
-#define PLANE_WM_EN (1 << 31)
-#define PLANE_WM_IGNORE_LINES (1 << 30)
-#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
-#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
-
-#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
-#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
-#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
-#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
-#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
-#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
-#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
-#define _PLANE_WM_BASE(pipe, plane) \
- _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-#define PLANE_WM(pipe, plane, level) \
- _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
-#define _PLANE_WM_SAGV_1(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
-#define _PLANE_WM_SAGV_2(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
-#define PLANE_WM_SAGV(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-#define _PLANE_WM_SAGV_TRANS_1(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
-#define _PLANE_WM_SAGV_TRANS_2(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
-#define PLANE_WM_SAGV_TRANS(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
-#define _PLANE_WM_TRANS_1(pipe) \
- _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
-#define _PLANE_WM_TRANS_2(pipe) \
- _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
-#define PLANE_WM_TRANS(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
-
/* define the Watermark register on Ironlake */
#define _WM0_PIPEA_ILK 0x45100
#define _WM0_PIPEB_ILK 0x45104
@@ -3988,6 +3073,7 @@
#define CUR_FBC_EN REG_BIT(31)
#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
+#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
#define _CURASURFLIVE 0x700ac /* g4x+ */
#define _CURBCNTR 0x700c0
#define _CURBBASE 0x700c4
@@ -4002,6 +3088,7 @@
#define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS)
#define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE)
#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A)
+#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A)
#define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
#define CURSOR_A_OFFSET 0x70080
@@ -4654,8 +3741,16 @@
#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
+#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
+#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
+#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
#define _PLANE_BUF_CFG_1_A 0x7027c
#define _PLANE_BUF_CFG_2_A 0x7037c
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
+#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
+#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
+#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
@@ -4799,28 +3894,12 @@
#define PLANE_SURFLIVE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
-#define _PLANE_BUF_CFG_1_B 0x7127c
-#define _PLANE_BUF_CFG_2_B 0x7137c
-/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
-#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
-#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
-#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
-#define _PLANE_BUF_CFG_1(pipe) \
- _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
-#define _PLANE_BUF_CFG_2(pipe) \
- _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
-#define PLANE_BUF_CFG(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
-
-#define _PLANE_NV12_BUF_CFG_1_B 0x71278
-#define _PLANE_NV12_BUF_CFG_2_B 0x71378
-#define _PLANE_NV12_BUF_CFG_1(pipe) \
- _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
-#define _PLANE_NV12_BUF_CFG_2(pipe) \
- _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
-#define PLANE_NV12_BUF_CFG(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+#define _PLANE_CHICKEN_1_B 0x7126c
+#define _PLANE_CHICKEN_2_B 0x7136c
+#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
+#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
+#define PLANE_CHICKEN(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
#define _PLANE_AUX_DIST_1_B 0x711c0
#define _PLANE_AUX_DIST_2_B 0x712c0
@@ -4859,56 +3938,6 @@
#define PLANE_COLOR_CTL(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
-#define _SEL_FETCH_PLANE_BASE_1_A 0x70890
-#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
-#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
-#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0
-#define _SEL_FETCH_PLANE_BASE_5_A 0x70920
-#define _SEL_FETCH_PLANE_BASE_6_A 0x70940
-#define _SEL_FETCH_PLANE_BASE_7_A 0x70960
-#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
-#define _SEL_FETCH_PLANE_BASE_1_B 0x71890
-
-#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
- _SEL_FETCH_PLANE_BASE_1_A, \
- _SEL_FETCH_PLANE_BASE_2_A, \
- _SEL_FETCH_PLANE_BASE_3_A, \
- _SEL_FETCH_PLANE_BASE_4_A, \
- _SEL_FETCH_PLANE_BASE_5_A, \
- _SEL_FETCH_PLANE_BASE_6_A, \
- _SEL_FETCH_PLANE_BASE_7_A, \
- _SEL_FETCH_PLANE_BASE_CUR_A)
-#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
-#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
- _SEL_FETCH_PLANE_BASE_1_A + \
- _SEL_FETCH_PLANE_BASE_A(plane))
-
-#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
-#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
- _SEL_FETCH_PLANE_CTL_1_A - \
- _SEL_FETCH_PLANE_BASE_1_A)
-#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
-
-#define _SEL_FETCH_PLANE_POS_1_A 0x70894
-#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
- _SEL_FETCH_PLANE_POS_1_A - \
- _SEL_FETCH_PLANE_BASE_1_A)
-
-#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
-#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
- _SEL_FETCH_PLANE_SIZE_1_A - \
- _SEL_FETCH_PLANE_BASE_1_A)
-
-#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
-#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
- _SEL_FETCH_PLANE_OFFSET_1_A - \
- _SEL_FETCH_PLANE_BASE_1_A)
-
-/* SKL new cursor registers */
-#define _CUR_BUF_CFG_A 0x7017c
-#define _CUR_BUF_CFG_B 0x7117c
-#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
-
/* VBIOS regs */
#define VGACNTRL _MMIO(0x71400)
# define VGA_DISP_DISABLE (1 << 31)
@@ -4938,14 +3967,6 @@
#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
-#define FDI_PLL_BIOS_0 _MMIO(0x46000)
-#define FDI_PLL_FB_CLOCK_MASK 0xff
-#define FDI_PLL_BIOS_1 _MMIO(0x46004)
-#define FDI_PLL_BIOS_2 _MMIO(0x46008)
-#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
-#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
-#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
-
#define PCH_3DCGDIS0 _MMIO(0x46020)
# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
@@ -4953,12 +3974,6 @@
#define PCH_3DCGDIS1 _MMIO(0x46024)
# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
-#define FDI_PLL_FREQ_CTL _MMIO(0x46030)
-#define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
-#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
-#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
-
-
#define _PIPEA_DATA_M1 0x60030
#define _PIPEA_DATA_N1 0x60034
#define _PIPEA_DATA_M2 0x60038
@@ -5511,6 +4526,7 @@
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
#define CHICKEN_MISC_2 _MMIO(0x42084)
+#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
#define GLK_CL2_PWR_DOWN (1 << 12)
@@ -5581,30 +4597,6 @@
#define DISP_DATA_PARTITION_5_6 (1 << 6)
#define DISP_IPC_ENABLE (1 << 3)
-/*
- * The below are numbered starting from "S1" on gen11/gen12, but starting
- * with display 13, the bspec switches to a 0-based numbering scheme
- * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
- * We'll just use the 0-based numbering here for all platforms since it's the
- * way things will be named by the hardware team going forward, plus it's more
- * consistent with how most of the rest of our registers are named.
- */
-#define _DBUF_CTL_S0 0x45008
-#define _DBUF_CTL_S1 0x44FE8
-#define _DBUF_CTL_S2 0x44300
-#define _DBUF_CTL_S3 0x44304
-#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
- _DBUF_CTL_S0, \
- _DBUF_CTL_S1, \
- _DBUF_CTL_S2, \
- _DBUF_CTL_S3))
-#define DBUF_POWER_REQUEST REG_BIT(31)
-#define DBUF_POWER_STATE REG_BIT(30)
-#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
-#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
-#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
-#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
-
#define GEN7_MSG_CTL _MMIO(0x45010)
#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
@@ -6148,12 +5140,6 @@
#define LPT_PWM_GRANULARITY (1 << 5)
#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
-#define _FDI_RXA_CHICKEN 0xc200c
-#define _FDI_RXB_CHICKEN 0xc2010
-#define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
-#define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
-#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
-
#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
@@ -6163,127 +5149,6 @@
#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
-/* CPU: FDI_TX */
-#define _FDI_TXA_CTL 0x60100
-#define _FDI_TXB_CTL 0x61100
-#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
-#define FDI_TX_DISABLE (0 << 31)
-#define FDI_TX_ENABLE (1 << 31)
-#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
-#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
-#define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
-#define FDI_LINK_TRAIN_NONE (3 << 28)
-#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
-#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
-#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
-#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
-#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
-#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
-#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
-#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
-/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
- SNB has different settings. */
-/* SNB A-stepping */
-#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
-#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
-#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
-#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
-/* SNB B-stepping */
-#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
-#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
-#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
-#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
-#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
-#define FDI_DP_PORT_WIDTH_SHIFT 19
-#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
-#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
-#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
-/* Ironlake: hardwired to 1 */
-#define FDI_TX_PLL_ENABLE (1 << 14)
-
-/* Ivybridge has different bits for lolz */
-#define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
-#define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
-#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
-#define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
-
-/* both Tx and Rx */
-#define FDI_COMPOSITE_SYNC (1 << 11)
-#define FDI_LINK_TRAIN_AUTO (1 << 10)
-#define FDI_SCRAMBLING_ENABLE (0 << 7)
-#define FDI_SCRAMBLING_DISABLE (1 << 7)
-
-/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
-#define _FDI_RXA_CTL 0xf000c
-#define _FDI_RXB_CTL 0xf100c
-#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
-#define FDI_RX_ENABLE (1 << 31)
-/* train, dp width same as FDI_TX */
-#define FDI_FS_ERRC_ENABLE (1 << 27)
-#define FDI_FE_ERRC_ENABLE (1 << 26)
-#define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
-#define FDI_8BPC (0 << 16)
-#define FDI_10BPC (1 << 16)
-#define FDI_6BPC (2 << 16)
-#define FDI_12BPC (3 << 16)
-#define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
-#define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
-#define FDI_RX_PLL_ENABLE (1 << 13)
-#define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
-#define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
-#define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
-#define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
-#define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
-#define FDI_PCDCLK (1 << 4)
-/* CPT */
-#define FDI_AUTO_TRAINING (1 << 10)
-#define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
-#define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
-#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
-#define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
-#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
-
-#define _FDI_RXA_MISC 0xf0010
-#define _FDI_RXB_MISC 0xf1010
-#define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
-#define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
-#define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
-#define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
-#define FDI_RX_TP1_TO_TP2_48 (2 << 20)
-#define FDI_RX_TP1_TO_TP2_64 (3 << 20)
-#define FDI_RX_FDI_DELAY_90 (0x90 << 0)
-#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
-
-#define _FDI_RXA_TUSIZE1 0xf0030
-#define _FDI_RXA_TUSIZE2 0xf0038
-#define _FDI_RXB_TUSIZE1 0xf1030
-#define _FDI_RXB_TUSIZE2 0xf1038
-#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
-#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
-
-/* FDI_RX interrupt register format */
-#define FDI_RX_INTER_LANE_ALIGN (1 << 10)
-#define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */
-#define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */
-#define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
-#define FDI_RX_FS_CODE_ERR (1 << 6)
-#define FDI_RX_FE_CODE_ERR (1 << 5)
-#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
-#define FDI_RX_HDCP_LINK_FAIL (1 << 3)
-#define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
-#define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
-#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
-
-#define _FDI_RXA_IIR 0xf0014
-#define _FDI_RXA_IMR 0xf0018
-#define _FDI_RXB_IIR 0xf1014
-#define _FDI_RXB_IMR 0xf1018
-#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
-#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
-
-#define FDI_PLL_CTL_1 _MMIO(0xfe000)
-#define FDI_PLL_CTL_2 _MMIO(0xfe004)
-
#define _PCH_DP_B 0xe4100
#define PCH_DP_B _MMIO(_PCH_DP_B)
#define _PCH_DPB_AUX_CH_CTL 0xe4110
@@ -7653,62 +6518,6 @@ enum skl_power_gate {
#define OROM_OFFSET _MMIO(0x1020c0)
#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
-/* This register controls the Display State Buffer (DSB) engines. */
-#define _DSBSL_INSTANCE_BASE 0x70B00
-#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
- (pipe) * 0x1000 + (id) * 0x100)
-#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
-#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
-#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
-#define DSB_ENABLE REG_BIT(31)
-#define DSB_BUF_REITERATE REG_BIT(29)
-#define DSB_WAIT_FOR_VBLANK REG_BIT(28)
-#define DSB_WAIT_FOR_LINE_IN REG_BIT(27)
-#define DSB_HALT REG_BIT(16)
-#define DSB_NON_POSTED REG_BIT(8)
-#define DSB_STATUS_BUSY REG_BIT(0)
-#define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)
-#define DSB_MMIO_DEAD_CLOCKS_ENABLE REG_BIT(31)
-#define DSB_MMIO_DEAD_CLOCKS_COUNT_MASK REG_GENMASK(15, 8)
-#define DSB_MMIO_DEAD_CLOCKS_COUNT(x) REG_FIELD_PREP(DSB_MMIO_DEAD_CLOCK_COUNT_MASK, (x))
-#define DSB_MMIO_CYCLES_MASK REG_GENMASK(7, 0)
-#define DSB_MMIO_CYCLES(x) REG_FIELD_PREP(DSB_MMIO_CYCLES_MASK, (x))
-#define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)
-#define DSB_POLL_ENABLE REG_BIT(31)
-#define DSB_POLL_WAIT_MASK REG_GENMASK(30, 23)
-#define DSB_POLL_WAIT(x) REG_FIELD_PREP(DSB_POLL_WAIT_MASK, (x)) /* usec */
-#define DSB_POLL_COUNT_MASK REG_GENMASK(22, 15)
-#define DSB_POLL_COUNT(x) REG_FIELD_PREP(DSB_POLL_COUNT_MASK, (x))
-#define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)
-#define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
-#define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)
-#define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
-#define DSB_ATS_FAULT_INT_EN REG_BIT(20)
-#define DSB_GTT_FAULT_INT_EN REG_BIT(19)
-#define DSB_RSPTIMEOUT_INT_EN REG_BIT(18)
-#define DSB_POLL_ERR_INT_EN REG_BIT(17)
-#define DSB_PROG_INT_EN REG_BIT(16)
-#define DSB_ATS_FAULT_INT_STATUS REG_BIT(4)
-#define DSB_GTT_FAULT_INT_STATUS REG_BIT(3)
-#define DSB_RSPTIMEOUT_INT_STATUS REG_BIT(2)
-#define DSB_POLL_ERR_INT_STATUS REG_BIT(1)
-#define DSB_PROG_INT_STATUS REG_BIT(0)
-#define DSB_CURRENT_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x2c)
-#define DSB_RM_TIMEOUT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x30)
-#define DSB_RM_CLAIM_TIMEOUT REG_BIT(31)
-#define DSB_RM_READY_TIMEOUT REG_BIT(30)
-#define DSB_RM_CLAIM_TIMEOUT_COUNT_MASK REG_GENMASK(23, 16)
-#define DSB_RM_CLAIM_TIMEOUT_COUNT(x) REG_FIELD_PREP(DSB_RM_CLAIM_TIMEOUT_COUNT_MASK, (x)) /* clocks */
-#define DSB_RM_READY_TIMEOUT_VALUE_MASK REG_GENMASK(15, 0)
-#define DSB_RM_READY_TIMEOUT_VALUE(x) REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */
-#define DSB_RMTIMEOUTREG_CAPTURE(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34)
-#define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)
-#define DSB_PMCTRL_2(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c)
-#define DSB_PF_LN_LOWER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x40)
-#define DSB_PF_LN_UPPER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x44)
-#define DSB_BUFRPT_CNT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x48)
-#define DSB_CHICKEN(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0)
-
#define CLKREQ_POLICY _MMIO(0x101038)
#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
@@ -7720,26 +6529,18 @@ enum skl_power_gate {
#define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A)
#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
-#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
-#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
-#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
-#define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
-#define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
-
-#define MTL_LATENCY_SAGV _MMIO(0x4578b)
-#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
-
#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
-#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2)
+#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
+#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
#define MTL_TRCD_MASK REG_GENMASK(31, 24)
#define MTL_TRP_MASK REG_GENMASK(23, 16)
#define MTL_DCLK_MASK REG_GENMASK(15, 0)
-#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2)
+#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
#define MTL_TRAS_MASK REG_GENMASK(16, 8)
#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.