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| author |   Luca Coelho <luciano.coelho@intel.com> | 2023-09-19 12:21:20 -0700 |
|---|---|---|
| committer |   Lucas De Marchi <lucas.demarchi@intel.com> | 2023-09-21 08:18:06 -0700 |
| commit | 6f35a04fd6636d749cb6dd3a937061ed4e7deb16 (patch) | |
| tree | 16223e806e76394b5b4a8c1ec18ddbb01ac6e3d3 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/xe2lpd: Handle port AUX interrupts (diff) | |
| download | wireguard-linux-6f35a04fd6636d749cb6dd3a937061ed4e7deb16.tar.xz wireguard-linux-6f35a04fd6636d749cb6dd3a937061ed4e7deb16.zip | |
drm/i915/xe2lpd: Read pin assignment from IOM
Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.
We use the pin assignment to decide the maximum lane count. So, to
support this change, add a new lnl_tc_port_get_max_lane_count() function
that reads from the TCSS_DDI_STATUS register and decides the maximum
lane count based on that.
BSpec: 69594
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-14-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 467edc6f9e39..d67f381050dc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6349,6 +6349,7 @@ enum skl_power_gate { #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ _TCSS_DDI_STATUS_1, \ _TCSS_DDI_STATUS_2)) +#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25) #define TCSS_DDI_STATUS_READY REG_BIT(2) #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) |