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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-04-18 20:55:19 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-04-20 15:17:06 +0300 |
| commit | e27525cc805548eaaa9d0cb8e8f0f181e9cd5390 (patch) | |
| tree | c7b7a3f50ac3648174bad52f62c5de9eda2acd79 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Use REG_BIT() & co for the pre-ilk pfit registers (diff) | |
| download | wireguard-linux-e27525cc805548eaaa9d0cb8e8f0f181e9cd5390.tar.xz wireguard-linux-e27525cc805548eaaa9d0cb8e8f0f181e9cd5390.zip | |
drm/i915: Namespace pfit registers properly
Give the PFIT_CONTROL bits a consistent namespace.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230418175528.13117-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f1e0fa8c17ac..639a150110c2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2339,13 +2339,13 @@ #define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0) #define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1) #define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2) -#define VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */ -#define VERT_INTERP_BILINEAR REG_FIELD_PREP(VERT_INTERP_MASK, 1) -#define VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */ -#define HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */ -#define HORIZ_INTERP_BILINEAR REG_FIELD_PREP(HORIZ_INTERP_MASK, 1) -#define HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ -#define PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ +#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */ +#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1) +#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */ +#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */ +#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1) +#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ +#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ |