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authorRodrigo Vivi <rodrigo.vivi@intel.com>2017-07-06 13:41:13 -0700
committerRodrigo Vivi <rodrigo.vivi@intel.com>2017-07-07 09:13:35 -0700
commit35ceabf3cdb557b23bbc09f0b6f7bb2b545185b1 (patch)
tree25d9710007c45ab88510b33536d9b5aeb0909a22 /drivers/gpu/drm/i915/i915_sysfs.c
parentdrm/i915/cnl: Gen10 render context size. (diff)
downloadwireguard-linux-35ceabf3cdb557b23bbc09f0b6f7bb2b545185b1.tar.xz
wireguard-linux-35ceabf3cdb557b23bbc09f0b6f7bb2b545185b1.zip
drm/i915/cnl: Inherit RPS stuff from previous platforms.
Apparently no change on RPS stuff from previous platforms. v2: Merging to rps related patches in one and also adding missed cases. Cc: David Weinehall <david.weinehall@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1499373673-25066-1-git-send-email-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_sysfs.c')
-rw-r--r--drivers/gpu/drm/i915/i915_sysfs.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 3736c9f79197..7fcf00622c4c 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -253,7 +253,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
} else {
u32 rpstat = I915_READ(GEN6_RPSTAT1);
- if (IS_GEN9(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 9)
ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;